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charset=UTF-8 Date: Wed, 26 Aug 2026 20:24:52 +0900 Message-Id: Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v8 1/1] rust: pci: add extended capability and SR-IOV support From: "Alexandre Courbot" To: "Zhi Wang" References: <20260818084633.1673214-1-zhiw@nvidia.com> <20260818084633.1673214-2-zhiw@nvidia.com> In-Reply-To: <20260818084633.1673214-2-zhiw@nvidia.com> X-ClientProxiedBy: OSTP286CA0112.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:225::12) To MW4PR12MB6873.namprd12.prod.outlook.com (2603:10b6:303:20c::17) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW4PR12MB6873:EE_|PH8PR12MB6937:EE_ X-MS-Office365-Filtering-Correlation-Id: 538e126e-9444-400e-2ce3-08df0364a7ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|23010399003|1800799024|366016|10070799003|6133799003|10067099003|11063799006|4143699003|56012099006|22082099003|18002099003; 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Expose > this information through the Rust PCI abstraction so drivers can use the > existing typed configuration-space accessors instead of raw bindings. > > Define ExtCapability to associate a capability ID with a register layout, > and add ConfigSpace::find_ext_capability() to locate and project that > layout. Bound the view at the next capability or the end of extended > configuration space. Add ExtSriovRegs and a decoded VF BAR iterator that > reads and validates all six VF BAR register slots up front, yields decode= d > BAR addresses and widths in logical order, and keeps the raw > configuration-space slot advancement internal. Since PCI_EXT_CAP_NEXT() i= s > a function-like macro, expose it through a Rust helper. > > Link: https://lore.kernel.org/rust-for-linux/20260804161612.776752-1-zhiw= @nvidia.com/ > Cc: Alexandre Courbot > Cc: Gary Guo > Signed-off-by: Zhi Wang > --- > rust/helpers/pci.c | 5 + > rust/kernel/pci.rs | 8 + > rust/kernel/pci/cap.rs | 329 +++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 342 insertions(+) > create mode 100644 rust/kernel/pci/cap.rs > > diff --git a/rust/helpers/pci.c b/rust/helpers/pci.c > index 4ebf256dff23..b946b14d79e4 100644 > --- a/rust/helpers/pci.c > +++ b/rust/helpers/pci.c > @@ -24,6 +24,11 @@ __rust_helper bool rust_helper_dev_is_pci(const struct= device *dev) > return dev_is_pci(dev); > } > =20 > +__rust_helper u32 rust_helper_pci_ext_cap_next(u32 header) > +{ > + return PCI_EXT_CAP_NEXT(header); > +} > + > #ifndef CONFIG_PCI_IOV > __rust_helper unsigned int > rust_helper_pci_sriov_get_totalvfs(struct pci_dev *pdev) > diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs > index 9f19ccd5905c..008c2770a3f3 100644 > --- a/rust/kernel/pci.rs > +++ b/rust/kernel/pci.rs > @@ -32,10 +32,18 @@ > }, > }; > =20 > +mod cap; > mod id; > mod io; > mod irq; > =20 > +pub use self::cap::{ > + ExtCapId, > + ExtCapability, > + ExtSriovCapability, > + ExtSriovRegs, > + ExtSriovVfBar, // > +}; > pub use self::id::{ > Class, > ClassMask, > diff --git a/rust/kernel/pci/cap.rs b/rust/kernel/pci/cap.rs > new file mode 100644 > index 000000000000..ddb3fd73e195 > --- /dev/null > +++ b/rust/kernel/pci/cap.rs > @@ -0,0 +1,329 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +//! PCI extended capability support. > + > +use super::{ > + io::ConfigSpaceBackend, > + ConfigSpace, > + Extended, // > +}; > +use crate::{ > + bindings, > + io::{ > + Io, > + IoBackend, > + Region, // > + }, > + num::Bounded, > + prelude::*, > +}; > + > +/// Number of VF BAR register slots in an SR-IOV capability. > +// CAST: `PCI_SRIOV_NUM_BARS` is the PCIe-specified number of VF BAR reg= ister slots and fits in > +// `usize`. > +const NUM_VF_BARS: usize =3D bindings::PCI_SRIOV_NUM_BARS as usize; > + > +/// PCI extended capability IDs. > +#[repr(transparent)] > +#[derive(Debug, Clone, Copy, PartialEq, Eq)] > +pub struct ExtCapId(u16); > + > +impl ExtCapId { > + /// Single Root I/O Virtualization. > + // CAST: PCI extended capability IDs are 16-bit values defined by th= e PCIe specification. > + pub const SRIOV: Self =3D Self(bindings::PCI_EXT_CAP_ID_SRIOV as u16= ); Coming back to comment on the conclusion: we have settled on a solution [1] to handle this nicely, but it is likely that your series will land before it. So meanwhile, please use the turbofish solution that I initially proposed: pub const SRIOV: Self =3D Self(casts::u32_into_u16::<{ bindings::PCI_EX= T_CAP_ID_SRIOV }>()); While it's a mouthful, [1] does remove `u32_into_u16`, which means we won't miss it and will need to update the code to use `const_as!` when applying. [1] https://lore.kernel.org/all/20260825-const_as-v1-1-1ce712225fe2@nvidia.= com/