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Thu, 27 Aug 2026 07:43:15 -0700 (PDT) Received: from localhost ([2001:4090:a244:80d4:489b:7642:1b32:84d6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b4942298fsm59654565e9.1.2026.08.27.07.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2026 07:43:14 -0700 (PDT) Mime-Version: 1.0 Content-Type: multipart/signed; boundary=e37bc370b29b2a3d5559411a9bc5b04170c252a07a6f0b6b5720295084c9; micalg=pgp-sha512; protocol="application/pgp-signature" Date: Thu, 27 Aug 2026 16:43:06 +0200 Message-Id: To: "Heinrich Schuchardt" , "Markus Schneider-Pargmann (TI)" Cc: "Lukasz Majewski" , "Tom Rini" , Subject: Re: [PATCH] clk: clk-uclass: Ignore -ENOSYS in clk_set_default_rates() From: "Markus Schneider-Pargmann" X-Mailer: aerc 0.21.0-146-gb5c16ebe1835 References: <20260827-v2026-10-next-topic-am45-ofupstream-clk-default-rates-enosys-v1-1-ce3b87667c09@baylibre.com> In-Reply-To: X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org --e37bc370b29b2a3d5559411a9bc5b04170c252a07a6f0b6b5720295084c9 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Hi Heinrich, On Thu Aug 27, 2026 at 2:49 PM CEST, Heinrich Schuchardt wrote: > On 8/27/26 14:36, Markus Schneider-Pargmann (TI) wrote: >> clk_set_default_parents() already ignores -ENOSYS from clk_set_parent(). >> Do the same for clk_set_default_rates() and rely on the earlier setup >> clock rates. >>=20 >> On am437x the cpsw switch has assigned-clock-rates for the RGMII clock. >> The divider delegates to a multiplier of the DPLL that has no set_rate >> and no delegation, so it returns -ENOSYS. >>=20 >> Signed-off-by: Markus Schneider-Pargmann (TI) >> --- >> drivers/clk/clk-uclass.c | 9 +++++++++ >> 1 file changed, 9 insertions(+) >>=20 >> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c >> index c33f415917e9..0069ce9a8875 100644 >> --- a/drivers/clk/clk-uclass.c >> +++ b/drivers/clk/clk-uclass.c >> @@ -359,6 +359,15 @@ static int clk_set_default_rates(struct udevice *de= v, >> =20 >> ret =3D clk_set_rate(c, rates[index]); >> =20 >> + /* >> + * Not all drivers/clocks support setting the rate (as of now). >> + * Ignore that and keep the rate set by an earlier boot stage. >> + */ >> + if (ret =3D=3D -ENOSYS) { > > In include struct clk_ops is incompletely documented. > > It is undefined which error code might indicate what. > This might be handled differently in different drivers. Thanks for your feedback! This patch is more about handling what clk_set_rate() returns than what the clk drivers return in set_rate(). clk_set_rate() itself has a check if CLK_SET_RATE_PARENT is unset and returns -ENOSYS otherwise if it couldn't find a suitable set_rate: /* Try to find parents which can set rate */ while (!ops->set_rate) { ... if (!(clkp->flags & CLK_SET_RATE_PARENT)) return -ENOSYS; ... } > > E.g. zynq_clk_set_rate() returns ENXIO if there is no set rate=20 > functionality. > > Please, complete the description of struct clk_ops, check what all clock= =20 > drivers do, and harmonize the return codes before adding this change. > > The struct clk_ops documentation should explicitly mention how error=20 > codes are handled by the uclass. set_rate is also already documented in clk-uclass.h: /** * set_rate() - Set current clock rate. * @clk: The clock to manipulate. * @rate: New clock rate in Hz. ... * Return: * * The new rate on success * * -%ENOSYS if this function is not implemented for @clk * * -%ENOENT if @clk->id is invalid. Prefer using an assert instead, and= doing * this check in request(). * * -%EINVAL if @rate is not valid for @clk. * * Another negative error value (such as %EIO or %ECOMM) if the rate co= uld * not be set due to a bus error. */ ulong set_rate(struct clk *clk, ulong rate); Best Markus --e37bc370b29b2a3d5559411a9bc5b04170c252a07a6f0b6b5720295084c9 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iKMEABYKAEsWIQSJYVVm/x+5xmOiprOFwVZpkBVKUwUCapBM+hsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDIRHG1zcEBiYXlsaWJyZS5jb20ACgkQhcFWaZAVSlO3 aAEA8CqSR/83mApJc+fmwwLBnDGl2RG1xbS1qqqhGdgGgRcBANOjvxR6yXbifONC FnHkX0e0x4QsARofM+RVLt9ObLcK =lUZ+ -----END PGP SIGNATURE----- --e37bc370b29b2a3d5559411a9bc5b04170c252a07a6f0b6b5720295084c9--