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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Sun Aug 9, 2026 at 9:14 PM CST, Cody Kang via B4 Relay wrote: > This series adds display support for the SpacemiT K3 [2], a RISC-V SoC: > a new DRM driver, a new PHY driver and three new bindings. > > The display path is three blocks deep: > > Saturn DPU -> Innosilicon DP/eDP controller -> Innosilicon DP PHY > > In v2, two major improvements: > > - Module unload is now robust. > - The bindings now require the controller's output port (port@1). > > The rest of the v2 changes please see below, with details in each patch's > changelog. > > Sashiko AI review contributed total review comments: 57 items, which I > accepted: 14 items. > > v2 repeated the full v1 test matrix on both boards, in built-in and > modular configurations, plus the new module load/unload rounds. > > The v1 cover letter follows below, unchanged, to provide some backgroud > (I can remove them from cover letter in next version): > > The Saturn DPU is SpacemiT's own display processing unit. It has a private > address translation unit and a command-list composer that replays a batch > of register writes when a flush is latched. It exposes one CRTC with one > primary plane. The K3 instantiates two DPUs, one per display path. > > The DPU driver arrives as five staged patches to keep each one a > reasonable size. The driver only becomes buildable with that last patch. > Bisect safe. > > The DP/eDP controller and its PHY are Innosilicon IP, also two instances > of each. An instance behaves as embedded DisplayPort or as external > DisplayPort purely according to what its output port is wired to, so the > bindings do not distinguish them. The PHY's registers are interleaved > with the controller's inside one MMIO window, which is why it is > described as a child node and shares the controller's regmap. > > The pixel clock is generated by the DP PHY's PLL, and the SoC's APMU > pixel-clock mux takes that PLL as an input. Rather than let the display > driver reach into PHY registers, the PHY registers its PLL as a clock > provider and the APMU mux is parented to it through the clock framework. > That is what patches 2, 4, 5 and 6 are for, and it is also what keeps the > APMU and the DP/eDP controller out of a devicetree provider cycle. > > As a first posting of the K3 display subsystem, this patchset supports: > a single primary plane per CRTC, linear RGB scanout (no plane scaling, > rotation, YUV or writeback). It does not support DSI, DSC or DP audio, > and link rates are capped at HBR2. > > Based on drm-misc-next at commit 5b9af25f2d0b ("accel/ivpu: Remove > unnecessary min_t()/max_t() usage"), v7.2-rc2 based. > > Testing this series needs a SpacemiT u-boot carrying display support > [1]. SpacemiT expects to add that support into an official u-boot > release in August 2026. > > Tested on two K3 boards: > > - Pico-ITX: an eDP panel and an external DisplayPort monitor. > - CoM260-IFX: DisplayPort only, no eDP. > > Note: The eDP panel DTS enablement is not part of this series; a separate > series will follow showing how eDP can be verified. > > What was run on both boards, with modetest from libdrm and with kmscube: > > - modetest -s, looped over 1920x1080, 1280x720 and 3840x2160 > on DisplayPort and 2560x1600 on eDP > - kmscube, on each head and on both at once > - hot-plug and sink swap on the DisplayPort connector Hi Cody, Tested the series on a K3 Pico-ITX (mainline v7.3-rc2 + these patches, display drivers built in). On the DisplayPort output: - modetest -s: 1920x1080 and 1280x720 OK (native 2560x1440 as well); 3840x2160 not tested: my monitor has no such mode. - kmscube: OK. - hot-plug: unplug/replug detected, output re-enables fine. Tested with the stock vendor U-Boot (2022.10); DP works fine with it. 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Sun, 13 Sep 2026 11:25:10 -0700 (PDT) X-Received: by 2002:a05:6a21:6016:b0:3cc:9618:f51a with SMTP id adf61e73a8af0-3db0e0ea40amr13919502637.8.1789323910173; Sun, 13 Sep 2026 11:25:10 -0700 (PDT) Received: from localhost ([155.117.96.35]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33ba4cf72dbsm23050289eec.3.2026.09.13.11.25.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 13 Sep 2026 11:25:09 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 14 Sep 2026 02:24:58 +0800 Message-Id: Cc: , , , , , , Subject: Re: [PATCH v2 00/17] drm/spacemit: add SpacemiT K3 display support From: "Ze Huang" To: , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Yixun Lan" , "Vinod Koul" , "Neil Armstrong" , "Haylen Chu" , "Michael Turquette" , "Stephen Boyd" , "Brian Masney" , "Philipp Zabel" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , "Yao Zi" , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Guodong Xu" X-Mailer: aerc 0.22.0.r10.g73f20125 References: <20260809-k3-display-v2-0-327d7910bf71@gmail.com> In-Reply-To: <20260809-k3-display-v2-0-327d7910bf71@gmail.com> X-Proofpoint-GUID: baYLr9eyO3Q_6rmn5y-1DL4DiMGTzIi9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTEzMDI1OSBTYWx0ZWRfXyjjmMqyRV+q3 kD6Wjp4aXwf7+AApgBiOrMkQ8zwXkkY1vscp7+s3CuUe4oAZPajQ7TYI/L12Iftu8skgAwn/65O wzF4Z678BGqFxBbKSoOzhMOWdpoJGFDH7+qtGXI2BJgfqEIXdeDzukq2Z2f3U2E9AijUacaAJpX hjdW5X0UkhVFI0ITPPJmSICl+iBNI7yCL7c294+R++h83wxWptYu61V4G6H6UywC8eoocG+p3mO MowxKGm/AJNeDEfM/L0CleDjOqzegDK3LIs6OBczb+lyCZZhdbOin37bw/Zx1SgWdAYAIyASYVY Mf1iHXJEZsCRbrNOT62LytmCbWTlQ4otAeFRTTu71iOuxdCrmoMMeZpWCg5JSCEQNSxOXiV7baN wMhjM+B7fpVSiRR1S8P0QI8anJ+RRxJ/WNvyzwQN7/of5MRGPYyFOgd4PZ2wsCXDWIbNb3Ygg6w 05A5n10gJ5gfJkF3Ffw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTEzMDI1OSBTYWx0ZWRfX3UdQCccVIek1 YZAT/2xPTgqc9OCEUXKLFpyVE94Ncj/OLY94TQU0iSySTmElUzTaoVeOd6ntAWg4N4+A3m2zzGb B52R/1YB5hZUhApWR3G81pTls9JgWJY= X-Proofpoint-ORIG-GUID: baYLr9eyO3Q_6rmn5y-1DL4DiMGTzIi9 X-Authority-Analysis: v=2.4 cv=PsUG/AM3 c=1 sm=1 tr=0 ts=6aa6ea87 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ilsi1XWDFcrB9FjxRIUvHg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=rqWh80hda8-QOrsfWKMA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-13_06,2026-09-11_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 adultscore=0 clxscore=1011 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609130259 On Sun Aug 9, 2026 at 9:14 PM CST, Cody Kang via B4 Relay wrote: > This series adds display support for the SpacemiT K3 [2], a RISC-V SoC: > a new DRM driver, a new PHY driver and three new bindings. > > The display path is three blocks deep: > > Saturn DPU -> Innosilicon DP/eDP controller -> Innosilicon DP PHY > > In v2, two major improvements: > > - Module unload is now robust. > - The bindings now require the controller's output port (port@1). > > The rest of the v2 changes please see below, with details in each patch's > changelog. > > Sashiko AI review contributed total review comments: 57 items, which I > accepted: 14 items. > > v2 repeated the full v1 test matrix on both boards, in built-in and > modular configurations, plus the new module load/unload rounds. > > The v1 cover letter follows below, unchanged, to provide some backgroud > (I can remove them from cover letter in next version): > > The Saturn DPU is SpacemiT's own display processing unit. It has a privat= e > address translation unit and a command-list composer that replays a batch > of register writes when a flush is latched. It exposes one CRTC with one > primary plane. The K3 instantiates two DPUs, one per display path. > > The DPU driver arrives as five staged patches to keep each one a > reasonable size. The driver only becomes buildable with that last patch. > Bisect safe. > > The DP/eDP controller and its PHY are Innosilicon IP, also two instances > of each. An instance behaves as embedded DisplayPort or as external > DisplayPort purely according to what its output port is wired to, so the > bindings do not distinguish them. The PHY's registers are interleaved > with the controller's inside one MMIO window, which is why it is > described as a child node and shares the controller's regmap. > > The pixel clock is generated by the DP PHY's PLL, and the SoC's APMU > pixel-clock mux takes that PLL as an input. Rather than let the display > driver reach into PHY registers, the PHY registers its PLL as a clock > provider and the APMU mux is parented to it through the clock framework. > That is what patches 2, 4, 5 and 6 are for, and it is also what keeps the > APMU and the DP/eDP controller out of a devicetree provider cycle. > > As a first posting of the K3 display subsystem, this patchset supports: > a single primary plane per CRTC, linear RGB scanout (no plane scaling, > rotation, YUV or writeback). It does not support DSI, DSC or DP audio, > and link rates are capped at HBR2. > > Based on drm-misc-next at commit 5b9af25f2d0b ("accel/ivpu: Remove > unnecessary min_t()/max_t() usage"), v7.2-rc2 based. > > Testing this series needs a SpacemiT u-boot carrying display support > [1]. SpacemiT expects to add that support into an official u-boot > release in August 2026. > > Tested on two K3 boards: > > - Pico-ITX: an eDP panel and an external DisplayPort monitor. > - CoM260-IFX: DisplayPort only, no eDP. > > Note: The eDP panel DTS enablement is not part of this series; a separate > series will follow showing how eDP can be verified. > > What was run on both boards, with modetest from libdrm and with kmscube: > > - modetest -s, looped over 1920x1080, 1280x720 and 3840x2160 > on DisplayPort and 2560x1600 on eDP > - kmscube, on each head and on both at once > - hot-plug and sink swap on the DisplayPort connector Hi Cody, Tested the series on a K3 Pico-ITX (mainline v7.3-rc2 + these patches, display drivers built in). On the DisplayPort output: - modetest -s: 1920x1080 and 1280x720 OK (native 2560x1440 as well); 3840x2160 not tested: my monitor has no such mode. - kmscube: OK. - hot-plug: unplug/replug detected, output re-enables fine. Tested with the stock vendor U-Boot (2022.10); DP works fine with it. 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Sun, 13 Sep 2026 11:25:10 -0700 (PDT) X-Received: by 2002:a05:6a21:6016:b0:3cc:9618:f51a with SMTP id adf61e73a8af0-3db0e0ea40amr13919502637.8.1789323910173; Sun, 13 Sep 2026 11:25:10 -0700 (PDT) Received: from localhost ([155.117.96.35]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33ba4cf72dbsm23050289eec.3.2026.09.13.11.25.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 13 Sep 2026 11:25:09 -0700 (PDT) Mime-Version: 1.0 Date: Mon, 14 Sep 2026 02:24:58 +0800 Message-Id: Cc: , , , , , , Subject: Re: [PATCH v2 00/17] drm/spacemit: add SpacemiT K3 display support From: "Ze Huang" To: , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Yixun Lan" , "Vinod Koul" , "Neil Armstrong" , "Haylen Chu" , "Michael Turquette" , "Stephen Boyd" , "Brian Masney" , "Philipp Zabel" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , "Yao Zi" , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Guodong Xu" X-Mailer: aerc 0.22.0.r10.g73f20125 References: <20260809-k3-display-v2-0-327d7910bf71@gmail.com> In-Reply-To: <20260809-k3-display-v2-0-327d7910bf71@gmail.com> X-Proofpoint-Spam-Info: AW1haW4tMjYwOTEzMDI1OSBTYWx0ZWRfX93GlP+ZYKs28 bbGaTno7aQ7nXnt6RSuj6y0YczwjuwLKoESRfzcDUt9U0tW7g3YBw9pcsZfx9y6hLByuxZLRFRr 6FwDr9kVKPGb4GG9v5Ow40/6RB0QLHM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTEzMDI1OSBTYWx0ZWRfXxg362FyPcuOl jZgCrEmTOdEk2E3008Hdjqx4zIvvDKQ+Xmxj6fd2gRQ0q9rdu1RpsWO0K2O5oC67UWOiVYc2Dyr QZf74sUr0cc7+zgQBaPX7fmPInUmzQvrsVSaldJLnXD2PB2OQDxF/Wh0Lme5T/+WLt0svr9J9P/ +GGEM7KeohWYFX8s2sC/O5kSi7SwE1SgmAlHFb8snAI5SiY0Q7YtblXsj9bBaroB7CrTPwYPFaN prW00XjZtQqQfmZvNQsqHKcPoYSfcObcVj2lC7CBlE6lp/imQ9MVEIz4gqrAmUae17waIG+77Bg GBNCbhjufL1MYDrbA7oq41ldQqYW3TRel0T/3sEWig52PgXykrhj5sKrgFiDo97ISCU4H3xKW/H Q70EwVmtytM7dcOdpg8hompguUWwOiyDv5fCtARYcKkssi7jrrknD5OLb9YR9mAASE9N7OKRZtt HpXiMzQCr1fwMnpldmA== X-Authority-Analysis: v=2.4 cv=IOSXmQvG c=1 sm=1 tr=0 ts=6aa6ea87 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=Ilsi1XWDFcrB9FjxRIUvHg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=rqWh80hda8-QOrsfWKMA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: VMZackLmicPBwM_5VLQqxQHWtQXXwdIf X-Proofpoint-GUID: VMZackLmicPBwM_5VLQqxQHWtQXXwdIf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-13_06,2026-09-11_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 phishscore=0 adultscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 clxscore=1011 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609130259 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260913_112513_311189_1A02C689 X-CRM114-Status: GOOD ( 30.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun Aug 9, 2026 at 9:14 PM CST, Cody Kang via B4 Relay wrote: > This series adds display support for the SpacemiT K3 [2], a RISC-V SoC: > a new DRM driver, a new PHY driver and three new bindings. > > The display path is three blocks deep: > > Saturn DPU -> Innosilicon DP/eDP controller -> Innosilicon DP PHY > > In v2, two major improvements: > > - Module unload is now robust. > - The bindings now require the controller's output port (port@1). > > The rest of the v2 changes please see below, with details in each patch's > changelog. > > Sashiko AI review contributed total review comments: 57 items, which I > accepted: 14 items. > > v2 repeated the full v1 test matrix on both boards, in built-in and > modular configurations, plus the new module load/unload rounds. > > The v1 cover letter follows below, unchanged, to provide some backgroud > (I can remove them from cover letter in next version): > > The Saturn DPU is SpacemiT's own display processing unit. It has a private > address translation unit and a command-list composer that replays a batch > of register writes when a flush is latched. It exposes one CRTC with one > primary plane. The K3 instantiates two DPUs, one per display path. > > The DPU driver arrives as five staged patches to keep each one a > reasonable size. The driver only becomes buildable with that last patch. > Bisect safe. > > The DP/eDP controller and its PHY are Innosilicon IP, also two instances > of each. An instance behaves as embedded DisplayPort or as external > DisplayPort purely according to what its output port is wired to, so the > bindings do not distinguish them. The PHY's registers are interleaved > with the controller's inside one MMIO window, which is why it is > described as a child node and shares the controller's regmap. > > The pixel clock is generated by the DP PHY's PLL, and the SoC's APMU > pixel-clock mux takes that PLL as an input. Rather than let the display > driver reach into PHY registers, the PHY registers its PLL as a clock > provider and the APMU mux is parented to it through the clock framework. > That is what patches 2, 4, 5 and 6 are for, and it is also what keeps the > APMU and the DP/eDP controller out of a devicetree provider cycle. > > As a first posting of the K3 display subsystem, this patchset supports: > a single primary plane per CRTC, linear RGB scanout (no plane scaling, > rotation, YUV or writeback). It does not support DSI, DSC or DP audio, > and link rates are capped at HBR2. > > Based on drm-misc-next at commit 5b9af25f2d0b ("accel/ivpu: Remove > unnecessary min_t()/max_t() usage"), v7.2-rc2 based. > > Testing this series needs a SpacemiT u-boot carrying display support > [1]. SpacemiT expects to add that support into an official u-boot > release in August 2026. > > Tested on two K3 boards: > > - Pico-ITX: an eDP panel and an external DisplayPort monitor. > - CoM260-IFX: DisplayPort only, no eDP. > > Note: The eDP panel DTS enablement is not part of this series; a separate > series will follow showing how eDP can be verified. > > What was run on both boards, with modetest from libdrm and with kmscube: > > - modetest -s, looped over 1920x1080, 1280x720 and 3840x2160 > on DisplayPort and 2560x1600 on eDP > - kmscube, on each head and on both at once > - hot-plug and sink swap on the DisplayPort connector Hi Cody, Tested the series on a K3 Pico-ITX (mainline v7.3-rc2 + these patches, display drivers built in). On the DisplayPort output: - modetest -s: 1920x1080 and 1280x720 OK (native 2560x1440 as well); 3840x2160 not tested: my monitor has no such mode. - kmscube: OK. - hot-plug: unplug/replug detected, output re-enables fine. Tested with the stock vendor U-Boot (2022.10); DP works fine with it. Tested-by: Ze Huang _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv