Re: [PATCH bpf-next 0/8] bpf: Add UHMUL and SHMUL instructions

["Alexei Starovoitov" <alexei.starovoitov@gmail.com>]

On Thu, Sep 17, 2026 at 12:17 PM Yazhou Tang <tangyazhou@zju.edu.cn> wrote:
> Patch 8/8 uses raw bytecode for UHMUL and SHMUL because LLVM support has
> not been merged yet. Once it is available, the raw encodings can be
> replaced with the uh*= and sh*= mnemonics. A draft LLVM implementation
> is available at:
>
>   https://github.com/ADSWT518/llvm-project/tree/bpf-hmul-insn
>
> We plan to finalize and submit it as an LLVM pull request after the
> kernel-side ISA changes are merged.

Pls send the LLVM PR now. It needs to be reviewed together
with kernel side.

I think it enables ISD::MULHU/MULHS legal under -mcpu=v4.
Does it mean that existing programs might generate new instructions
and stop loading on current kernels?
If so, we'd have to introduce -mcpu=v5 for that
and extra flag like we did for other insns.

>  arch/arm64/include/asm/insn.h                 |   4 +
>  arch/arm64/lib/insn.c                         |   6 +
>  arch/arm64/net/bpf_jit.h             
         |   6 +
>  arch/arm64/net/bpf_jit_comp.c                 |  15 +-
>  arch/loongarch/net/bpf_jit.c                  |   3 +
>  arch/mips/net/bpf_jit_comp32.c                |   3 +
>  arch/mips/net/bpf_jit_comp64.c                |   3 +
>  arch/parisc/net/bpf_jit_comp32.c              |   3 +
>  arch/parisc/net/bpf_jit_comp64.c              |   3 +
>  arch/powerpc/net/bpf_jit_comp32.c             |   3 +
>  arch/powerpc/net/bpf_jit_comp64.c             |   3 +
>  arch/riscv/net/bpf_jit.h                      |   5 +
>  arch/riscv/net/bpf_jit_comp32.c               |   3 +
>  arch/riscv/net/bpf_jit_comp64.c               |  18 +-

Pls cc arm64, riscv or other arch JIT maintainers on respin.
We need acks from them.