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b=Mc1hAmZgc8+lVJ1+HFuRcYjjVUlaTw+5EUfXLytohfZaC+x6SuW13WTO1WoNplG8Cj78EDFRgatZVWtl0BCqtoxDbVogya2gdwcQu9gIGAXXmf0BG/ny/ikJ3NEPnj+dxLGGbTIVecGqqH4O3xayn/4OcF3ib6TtsnLnU5EZQ9k= Authentication-Results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 21 Sep 2026 16:08:26 +0200 Message-Id: Subject: Re: [PATCH v2 2/6] automation/qtb: add jinja2 device trees for riscv64 smoke tests From: "Alejandro Vallejo" To: "Baptiste Le Duc" , Cc: "Doug Goldstein" , "Stefano Stabellini" X-Mailer: aerc 0.17.0 References: <1787823334.8631fc262581453bbf619ec5b2062170.1a04293255c000c4f3@vates.tech> <1787823788.8631fc262581453bbf619ec5b2062170.1a0429a1050000c4f3@vates.tech> In-Reply-To: <1787823788.8631fc262581453bbf619ec5b2062170.1a0429a1050000c4f3@vates.tech> X-ClientProxiedBy: MA2P292CA0024.ESPP292.PROD.OUTLOOK.COM (2603:10a6:250::6) To BY5PR12MB4999.namprd12.prod.outlook.com (2603:10b6:a03:1da::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY5PR12MB4999:EE_|DM6PR12MB4436:EE_ X-MS-Office365-Filtering-Correlation-Id: e64c50f4-f356-4559-f431-08df17e9d0b0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|23010399003|376014|10067099003|11063799006|6133799003|22082099003|18002099003|56012099006|4143699003; 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It varies per machine (hart count, MM= U > type), so a single static .dts cannot cover the test matrix. > > Add dts/qemu-host.dts.j2, a template of the QEMU virt platform in > aia=3Daplic-imsic mode: per-hart cpu/cpu-intc nodes, the M- and S-mode AP= LIC > and IMSIC pairs, CLINT and the ns16550a uart. It takes ncpus, mmu_type an= d > xen_bootargs as arguments. Alternatively, why not query it from qemu itself? See "-machine dumpdtb=3Ddump.dtb" in "qemu-smoke-dom0less-arm64.sh" Then you can use fdtput to add nodes as needed, with all hardware being consistent with QEMU without undue magic replacements. Having a configurable .dts seems like a silent mistake about to happen. Check out that file of arm automation for DTB manipulation. I think it's best if all DTB ports behave the same way. Cheers, Alejandro > > Values QEMU hardcodes are set as named constants matching their source > symbols (QEMU_UART0_IRQ, QEMU_IRQCHIP_NUM_SOURCES, ...) rather than > open-coded, so a QEMU-side change is easy to trace. > > The template is inert on its own: the generated dtb will be used in next > patch. > > Assisted-by: Claude:claude-opus-5 > Signed-off-by: Baptiste Le Duc > --- > .../scripts/qtb/riscv/dts/qemu-host.dts.j2 | 160 ++++++++++++++++++ > 1 file changed, 160 insertions(+) > create mode 100644 automation/scripts/qtb/riscv/dts/qemu-host.dts.j2 > > diff --git a/automation/scripts/qtb/riscv/dts/qemu-host.dts.j2 b/automati= on/scripts/qtb/riscv/dts/qemu-host.dts.j2 > new file mode 100644 > index 0000000000..13a8e983ce > --- /dev/null > +++ b/automation/scripts/qtb/riscv/dts/qemu-host.dts.j2 > @@ -0,0 +1,160 @@ > +/dts-v1/; > + > +{#- > + * Jinja2 QEMU "virt" platform device tree for Xen RISC-V tests. > + * > + * Interrupt controller: APLIC in MSI mode + IMSIC > + * (QEMU -M virt,aia=3Daplic-imsic). > + * > + * Rendered by xen_dt.py. > + * > + * Variables: > + * ncpus - number of physical harts (int, >=3D 1= ) > + * mmu_type - Xen host MMU type, e.g. "sv39" (string) > + * xen_bootargs - Xen command line (string) > + * > + * Per-hart nodes are labelled cpu / cpu_intc and referenced with = &label. > + * > + * No `aia-guests=3DN`, so no VS-mode guest files: IMSIC reg size is > + * ncpus * page size. > +-#} > +{#- Values QEMU hardcodes, need to be described to Xen -#} > +{%- set QEMU_TIMEBASE_FREQUENCY =3D 10000000 %} {#- RISCV_ACLINT_DEFAU= LT_TIMEBASE_FREQ -#} > +{%- set QEMU_IRQCHIP_NUM_SOURCES =3D 96 %} {#- VIRT_IRQCHIP_NUM_S= OURCES (virt.h) -#} > +{%- set QEMU_IRQCHIP_NUM_MSIS =3D 255 %} {#- VIRT_IRQCHIP_NUM_M= SIS -#} > +{%- set QEMU_UART_CLOCK_FREQUENCY =3D 3686400 %} {#- create_fdt_uart() = -#} > +{%- set QEMU_UART0_IRQ =3D 10 %} {#- UART0_IRQ -#} > +{%- set QEMU_IMSIC_PAGE_SZ =3D 0x1000 %} {#- IMSIC_MMIO_PAGE_SZ= -#} > + > +{%- set IRQ_TYPE_LEVEL_HIGH =3D 4 %} > +{%- set APLIC_IRQ_CELLS =3D 2 %} > + > +{%- set IRQ_M_SOFT =3D 3 %} > +{%- set IRQ_M_TIMER =3D 7 %} > +{%- set IRQ_S_EXT =3D 9 %} > +{%- set IRQ_M_EXT =3D 11 %} > + > +/ { > + #address-cells =3D <0x02>; > + #size-cells =3D <0x02>; > + compatible =3D "riscv-virtio"; > + model =3D "riscv-virtio,qemu"; > + > + memory@80000000 { > + device_type =3D "memory"; > + reg =3D <0x00 0x80000000 0x00 0x80000000>; > + }; > + > + cpus { > + #address-cells =3D <0x01>; > + #size-cells =3D <0x00>; > + timebase-frequency =3D <{{ QEMU_TIMEBASE_FREQUENCY }}>; > +{% for i in range(ncpus) %} > + cpu{{ i }}: cpu@{{ i }} { > + device_type =3D "cpu"; > + reg =3D <0x{{ '%x' % i }}>; > + status =3D "okay"; > + compatible =3D "riscv"; > + riscv,cbop-block-size =3D <0x40>; > + riscv,cboz-block-size =3D <0x40>; > + riscv,cbom-block-size =3D <0x40>; > + riscv,isa =3D "rv64imafdch_zicntr_zicsr_zifencei_zihintpause= _zihpm_zba_zbb_zbs_smstateen_svpbmt_smaia_ssaia"; > + mmu-type =3D "riscv,{{ mmu_type }}"; > + > + cpu{{ i }}_intc: interrupt-controller@{{ i }} { > + #interrupt-cells =3D <0x01>; > + interrupt-controller; > + compatible =3D "riscv,cpu-intc"; > + }; > + }; > +{% endfor %} > + cpu-map { > + > + cluster0 { > +{% for i in range(ncpus) %} > + core{{ i }} { > + cpu =3D <&cpu{{ i }}>; > + }; > +{% endfor %} > + }; > + }; > + }; > + > + soc { > + #address-cells =3D <0x02>; > + #size-cells =3D <0x02>; > + compatible =3D "simple-bus"; > + ranges; > + > + serial@10000000 { > + interrupts =3D <{{ QEMU_UART0_IRQ }} {{ IRQ_TYPE_LEVEL_HIGH = }}>; > + interrupt-parent =3D <&aplic_s>; > + clock-frequency =3D <{{ QEMU_UART_CLOCK_FREQUENCY }}>; > + reg =3D <0x00 0x10000000 0x00 0x100>; > + compatible =3D "ns16550a"; > + }; > + > + aplic_s: aplic@d000000 { > + riscv,num-sources =3D <{{ QEMU_IRQCHIP_NUM_SOURCES }}>; > + reg =3D <0x00 0xd000000 0x00 0x8000>; > + msi-parent =3D <&imsic_s>; > + interrupt-controller; > + #interrupt-cells =3D <{{ APLIC_IRQ_CELLS }}>; > + compatible =3D "riscv,aplic"; > + }; > + > + aplic@c000000 { > + riscv,delegate =3D <&aplic_s 0x01 {{ QEMU_IRQCHIP_NUM_SOURCE= S }}>; > + riscv,children =3D <&aplic_s>; > + riscv,num-sources =3D <{{ QEMU_IRQCHIP_NUM_SOURCES }}>; > + reg =3D <0x00 0xc000000 0x00 0x8000>; > + msi-parent =3D <&imsic_m>; > + interrupt-controller; > + #interrupt-cells =3D <{{ APLIC_IRQ_CELLS }}>; > + compatible =3D "riscv,aplic"; > + }; > + > + imsic_s: imsics@28000000 { > + riscv,num-ids =3D <{{ QEMU_IRQCHIP_NUM_MSIS }}>; > + reg =3D <0x00 0x28000000 0x00 0x{{ '%x' % (ncpus * QEMU_IMSI= C_PAGE_SZ) }}>; > + interrupts-extended =3D < > + {%- for i in range(ncpus) %} > + &cpu{{ i }}_intc {{ IRQ_S_EXT }} > + {%- endfor %} > + >; > + msi-controller; > + interrupt-controller; > + #interrupt-cells =3D <0x00>; > + compatible =3D "riscv,imsics"; > + }; > + > + imsic_m: imsics@24000000 { > + riscv,num-ids =3D <{{ QEMU_IRQCHIP_NUM_MSIS }}>; > + reg =3D <0x00 0x24000000 0x00 0x{{ '%x' % (ncpus * QEMU_IMSI= C_PAGE_SZ) }}>; > + interrupts-extended =3D < > + {%- for i in range(ncpus) %} > + &cpu{{ i }}_intc {{ IRQ_M_EXT }} > + {%- endfor %} > + >; > + msi-controller; > + interrupt-controller; > + #interrupt-cells =3D <0x00>; > + compatible =3D "riscv,imsics"; > + }; > + > + clint@2000000 { > + interrupts-extended =3D < > + {%- for i in range(ncpus) %} > + &cpu{{ i }}_intc {{ IRQ_M_SOFT }} &cpu{{ i }}_intc {= { IRQ_M_TIMER }} > + {%- endfor %} > + >; > + reg =3D <0x00 0x2000000 0x00 0x10000>; > + compatible =3D "sifive,clint0", "riscv,clint0"; > + }; > + }; > + > + chosen { > + stdout-path =3D "/soc/serial@10000000"; > + xen,xen-bootargs =3D "{{ xen_bootargs }}"; > + }; > +};