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Thu, 01 Oct 2026 10:02:33 -0700 (PDT) Received: from localhost ([2001:1970:3847:e000:1977:be2f:4a71:2892]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3a87e32c6ccsm470601fa.38.2026.10.01.10.02.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 01 Oct 2026 10:02:29 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 01 Oct 2026 13:02:25 -0400 Message-Id: To: "Alistair Francis" , "tgamblin@baylibre.com" , "qemu-devel@nongnu.org" From: "Trevor Gamblin" Subject: Re: [PATCH v2 2/2] target/riscv: add helper_tlb_flush_page(), use for sfence.vma with vaddr operand Cc: "palmer@dabbelt.com" , "qemu-riscv@nongnu.org" , "daniel.barboza@oss.qualcomm.com" , "chao.liu@processmission.com" , "liwei1518@gmail.com" , "zhiwei_liu@linux.alibaba.com" , X-Mailer: aerc 0.22.0 References: <20260904-riscv_tlb_page_flush-v2-0-defec3f29312@baylibre.com> <20260904-riscv_tlb_page_flush-v2-2-defec3f29312@baylibre.com> <322f18f233ae985970ba75eede7d3623110b13f3.camel@wdc.com> In-Reply-To: <322f18f233ae985970ba75eede7d3623110b13f3.camel@wdc.com> Received-SPF: pass client-ip=2a00:1450:4864:38::d; envelope-from=tgamblin@baylibre.com; helo=mail-lr2-x0d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu Oct 1, 2026 at 1:14 AM EDT, Alistair Francis wrote: > On Fri, 2026-09-04 at 14:43 -0400, Trevor Gamblin wrote: >> sfence.vma unconditionally called helper_tlb_flush(), regardless of >> the >> rs1 (vaddr) and rs2 (asid) operands, forcing a page-table walk on the >> next access. Create a page-level counterpart to helper_tlb_flush() >> called helper_tlb_flush_page(), and use it whenever rs1 !=3D 0, falling >> back to the existing full flush for rs1 =3D=3D 0. This makes RISC-V >> behaviour more similar to ARM's equivalent (tlbi_aa64_vae1_write), >> which >> already does tlb_flush_page_by_mmuidx() instead of a full flush. >>=20 >> Pass get_address(ctx, a->rs1, 0) to gen_helper_tlb_flush_page() >> rather >> than get_gpr(), so that the address being passed matches the current >> addr_xl width regardless of '-cpu' input. Otherwise, the raw register >> value can carry garbage above that width and never match the address >> the >> TLB entry was actually filled under, so the flush silently misses and >> a >> stale mapping survives. >>=20 >> Signed-off-by: Trevor Gamblin > > Reviewed-by: Alistair Francis > > Can you fixup sinval.vma and hinval.* as well please? Sure! I'm travelling next week, but I'll see if I can get patches written i= n downtime or right afterward. Trevor > > Alistair > >> --- >> =C2=A0target/riscv/helper.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 1 + >> =C2=A0target/riscv/tcg/insn_trans/trans_privileged.c.inc | 6 +++++- >> =C2=A0target/riscv/tcg/op_helper.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 | 6 ++++++ >> =C2=A03 files changed, 12 insertions(+), 1 deletion(-) >>=20 >> diff --git a/target/riscv/helper.h b/target/riscv/helper.h >> index 4fc2d3a155..652f85a5c7 100644 >> --- a/target/riscv/helper.h >> +++ b/target/riscv/helper.h >> @@ -137,6 +137,7 @@ DEF_HELPER_1(ctr_clear, void, env) >> =C2=A0DEF_HELPER_1(wfi, void, env) >> =C2=A0DEF_HELPER_1(wrs_nto, void, env) >> =C2=A0DEF_HELPER_1(tlb_flush, void, env) >> +DEF_HELPER_2(tlb_flush_page, void, env, tl) >> =C2=A0DEF_HELPER_1(tlb_flush_all, void, env) >> =C2=A0DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) >> =C2=A0/* Native Debug */ >> diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc >> b/target/riscv/tcg/insn_trans/trans_privileged.c.inc >> index a8eaccef67..8655fa332e 100644 >> --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc >> +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc >> @@ -155,7 +155,11 @@ static bool trans_sfence_vma(DisasContext *ctx, >> arg_sfence_vma *a) >> =C2=A0{ >> =C2=A0#ifndef CONFIG_USER_ONLY >> =C2=A0=C2=A0=C2=A0=C2=A0 decode_save_opc(ctx, 0); >> -=C2=A0=C2=A0=C2=A0 gen_helper_tlb_flush(tcg_env); >> +=C2=A0=C2=A0=C2=A0 if (a->rs1 =3D=3D 0) { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 gen_helper_tlb_flush(tcg_env= ); >> +=C2=A0=C2=A0=C2=A0 } else { >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 gen_helper_tlb_flush_page(tc= g_env, get_address(ctx, a->rs1, >> 0)); >> +=C2=A0=C2=A0=C2=A0 } >> =C2=A0=C2=A0=C2=A0=C2=A0 return true; >> =C2=A0#endif >> =C2=A0=C2=A0=C2=A0=C2=A0 return false; >> diff --git a/target/riscv/tcg/op_helper.c >> b/target/riscv/tcg/op_helper.c >> index 7f63f3ada5..178b4d271b 100644 >> --- a/target/riscv/tcg/op_helper.c >> +++ b/target/riscv/tcg/op_helper.c >> @@ -607,6 +607,12 @@ void helper_tlb_flush(CPURISCVState *env) >> =C2=A0=C2=A0=C2=A0=C2=A0 tlb_flush(cs); >> =C2=A0} >> =C2=A0 >> +void helper_tlb_flush_page(CPURISCVState *env, target_ulong addr) >> +{ >> +=C2=A0=C2=A0=C2=A0 check_sfence_vma(env, GETPC()); >> +=C2=A0=C2=A0=C2=A0 tlb_flush_page(env_cpu(env), addr); >> +} >> + >> =C2=A0void helper_tlb_flush_all(CPURISCVState *env) >> =C2=A0{ >> =C2=A0=C2=A0=C2=A0=C2=A0 CPUState *cs =3D env_cpu(env);