From: "Paul Louvel" <paul.louvel@bootlin.com>
To: "Geert Uytterhoeven" <geert@linux-m68k.org>,
"Paul Louvel" <paul.louvel@bootlin.com>
Cc: "Borislav Petkov" <bp@alien8.de>,
"Tony Luck" <tony.luck@intel.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>,
<linux-kernel@vger.kernel.org>,
<linux-renesas-soc@vger.kernel.org>, <linux-edac@vger.kernel.org>,
<devicetree@vger.kernel.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Miquel Raynal" <miquel.raynal@bootlin.com>,
"Herve Codina" <herve.codina@bootlin.com>,
"Wolfram Sang" <wsa+renesas@sang-engineering.com>
Subject: Re: [PATCH v6 3/3] ARM: dts: renesas: r9a06g032: add EDAC node
Date: Tue, 13 Oct 2026 13:57:56 +0200 [thread overview]
Message-ID: <DM3OXV8IQQKR.36V79A742H52F@bootlin.com> (raw)
In-Reply-To: <CAMuHMdV1nuiSAKbCrD0mWJX7rC4T=fxO5LC5ksRD440YSL_3cw@mail.gmail.com>
Hi Geert,
On Tue Oct 13, 2026 at 1:41 PM CEST, Geert Uytterhoeven wrote:
> Hi Paul,
>
> On Tue, 13 Oct 2026 at 12:45, Paul Louvel <paul.louvel@bootlin.com> wrote:
>> Add EDAC node to the SoC base device tree file.
>>
>> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>> Signed-off-by: Paul Louvel (Schneider Electric) <paul.louvel@bootlin.com>
>
> Thanks for your patch!
>
>> --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
>> +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
>> @@ -164,6 +164,15 @@ dmamux: dma-router@a0 {
>> };
>> };
>>
>> + edac: memory-controller@4000d000 {
>> + compatible = "renesas,r9a06g032-ddr-edac", "cdns,ddr-edac";
>> + reg = <0x4000d000 0x1000>;
>> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&sysctrl R9A06G032_CLK_DDRC>, <&sysctrl R9A06G032_HCLK_DDRC>;
>> + clock-names = "ddrc", "pclk";
>> + status = "disabled";
>
> Should this node be enabled by default, or am I too naive?
The bootloader will be responsible to initialize the DDR controller and enable
ECC if specified. On this specific platform (r9a06g032), ECC is disabled by
default.
Enabling the ECC require a specific property to be present under the controller
node in U-Boot. I think it make sense to keep it by default disabled.
>
>> + };
>> +
>> udc: usb@4001e000 {
>> compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf";
>> reg = <0x4001e000 0x2000>;
>>
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Paul Louvel, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
next prev parent reply other threads:[~2026-10-13 11:58 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 10:44 [PATCH v6 0/3] Add Renesas RZ/N1x EDAC driver Paul Louvel
2026-10-13 10:44 ` [PATCH v6 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC Paul Louvel
2026-10-13 10:44 ` [PATCH v6 2/3] EDAC/cadence: Add Cadence DDR EDAC driver Paul Louvel
2026-10-13 10:45 ` [PATCH v6 3/3] ARM: dts: renesas: r9a06g032: add EDAC node Paul Louvel
2026-10-13 11:41 ` Geert Uytterhoeven
2026-10-13 11:57 ` Paul Louvel [this message]
2026-10-13 13:52 ` Miquel Raynal
2026-10-13 14:14 ` Paul Louvel
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