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Mon, 19 Oct 2026 10:14:25 -0700 (PDT) Received: from localhost ([2001:1970:3847:e000:1977:be2f:4a71:2892]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5362a9c273esm105449611cf.20.2026.10.19.10.14.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Oct 2026 10:14:25 -0700 (PDT) X-Archived-By: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 19 Oct 2026 13:14:23 -0400 Message-Id: Cc: , , , , , , , To: "Wang Yechao" , , , From: "Trevor Gamblin" Subject: Re: [PATCH v2 0/2] target: riscv: support TLB page flush for sfence.vma X-Mailer: aerc 0.22.0 References: <20261008070029.20239-1-wang.yechao255@zte.com.cn> In-Reply-To: <20261008070029.20239-1-wang.yechao255@zte.com.cn> Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=tgamblin@baylibre.com; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_PASS,SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu Oct 8, 2026 at 3:00 AM EDT, Wang Yechao wrote: > Hi all, > > Patch 1 decides whether to use tlb_flush_page based on whether rs1 > is 0. This is similar to a patch I submitted last year [1]. Under > normal circumstances this works fine, but it can leave stale TLB > entries when the guest kernel uses THP. > > The reason is that with THP, the guest's mapping is at the PMD level. > When flushing the TLB, the guest executes sfence.vma only once for the > whole huge page, rather than 512 times to flush each individual 4K page. > Patch 1 does not account for this: it only flushes the single 4K page > corresponding to the address in rs1, leaving the other 511 pages of the > huge page with stale entries. As a result, guest memory access faults > can occur after Patch 1 is merged, unless huge-page TLB support is added > for the RISC-V TCG case. > > Please correct me if I've misunderstood anything. Hi, Thanks for letting me know about this. I'm working on a local test setup to= be able to reproduce the problem, and I'll look into a more complete fix if so= . > > [1] https://lore.kernel.org/qemu-devel/20250930174849833XG1Q1ETbNvg66WU2U= VBTV@zte.com.cn/ > > Yechao, > Regards