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Fri, 23 Oct 2026 03:22:13 -0700 (PDT) X-Received: by 2002:a05:6000:2310:b0:48b:f93:3b87 with SMTP id ffacd0b85a97d-48e3859ce44mr2921948f8f.30.1792750932850; Fri, 23 Oct 2026 03:22:12 -0700 (PDT) Received: from localhost ([213.175.46.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e38025e0esm4300291f8f.11.2026.10.23.03.22.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Oct 2026 03:22:12 -0700 (PDT) X-Archived-By: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 23 Oct 2026 12:22:11 +0200 Message-Id: Cc: "Brian Cain" , "Pierrick Bouvier" , Subject: Re: [PATCH] hw/intc/hex-l2vic: avoid shift into sign bit From: "Tommaso Califano" To: "Peter Maydell" , X-Mailer: aerc 0.22.0 References: <20261023084624.1063258-1-peter.maydell@linaro.org> In-Reply-To: <20261023084624.1063258-1-peter.maydell@linaro.org> Received-SPF: pass client-ip=170.10.133.124; envelope-from=tcalifano@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.339, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-16.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Fri Oct 23, 2026 at 10:46 AM CEST, Peter Maydell wrote: > In fastl2vic_write() we do: > val =3D 1 << (irq % 32); > > Because '1' is a signed integer, this can shift into the sign > bit of 'int'; the cast to uint64_t to assign to 'val' then > results in all the high bits being set. This happens to cause > no visible problems because l2vic_write never looks at those > bits, but it's obviously not intended. Use 1ULL so that we > do the shift as 64 bits unsigned. > > Resolves: Coverity CID 1685261 > Signed-off-by: Peter Maydell > --- > hw/intc/hex-l2vic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/intc/hex-l2vic.c b/hw/intc/hex-l2vic.c > index 736f1be3b1d..89b44200928 100644 > --- a/hw/intc/hex-l2vic.c > +++ b/hw/intc/hex-l2vic.c > @@ -381,7 +381,7 @@ static void fastl2vic_write(void *opaque, hwaddr offs= et, uint64_t val, > uint32_t cmd =3D (val >> 16) & 0x3; > uint32_t irq =3D val & 0x3ff; > uint32_t slice =3D (irq / 32) * 4; > - val =3D 1 << (irq % 32); > + val =3D 1ULL << (irq % 32); > =20 > if (cmd =3D=3D FASTL2VIC_ENABLE) { > l2vic_write(opaque, L2VIC_INT_ENABLE_SETn + slice, val, size= ); Not an expert, but LGTM. Reviewed-by: Tommaso Califano Regards, Tommaso