Re: [PATCH 2/4] gpu: nova-core: regs: add msgq v2 BAR0 register declarations

["Eliot Courtney" <ecourtney@nvidia.com>]

On Fri Oct 30, 2026 at 4:41 PM JST, Alexandre Courbot wrote:
> From: John Hubbard <jhubbard@nvidia.com>
>
> Msgq is the pair of ring buffers in shared memory through which the
> driver and GSP-RM communicate. The command queue carries commands from
> the driver to GSP-RM, and the message queue carries messages from GSP-RM
> to the driver. Each ring buffer has a write pointer and a read pointer.
>
> Msgq v0, which the r570 firmware uses, keeps both pointers of each ring
> buffer in that ring buffer's header, in shared memory. Msgq v2, which
> the r000 firmware uses, keeps the four pointers, two per ring buffer, in
> four BAR0 registers instead:
>
>     NV_PGSP_QUEUE_HEAD    command queue write pointer
>     NV_PGSP_QUEUE_TAIL    command queue read pointer
>     NV_PGSP_MSGQ_HEAD     message queue write pointer
>     NV_PGSP_MSGQ_TAIL     message queue read pointer
>
> The GSP numbers its queues 0 through 7, and each numbered queue is one
> such pair of ring buffers with its own four pointer registers, so the
> hardware has 32 pointer registers in all. Nova-core uses queue 0 only.
>
> A write to NV_PGSP_QUEUE_HEAD also interrupts the GSP. Msgq v0 uses that
> write as the doorbell, so nova-core already declares NV_PGSP_QUEUE_HEAD.
>
> Declare the other three, NV_PGSP_QUEUE_TAIL, NV_PGSP_MSGQ_HEAD and
> NV_PGSP_MSGQ_TAIL.
>
> All four registers are declared as the arrays of eight that the hardware
> defines, with the stride of 8 bytes at which the HEAD and TAIL registers
> of a queue interleave, as the NV_PFSP_* queue registers already are. The
> existing doorbell write names queue 0 explicitly.
>
> No functional change intended.
>
> [ acourbot: declare the registers as arrays of 8 with a stride of 8. ]
> [ acourbot: use "val" for the field name of NV_PGSP_MSGQ as per OpenRM. ]
>
> Assisted-by: LLM
> Signed-off-by: John Hubbard <jhubbard@nvidia.com>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---

Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>