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Tue, 03 Nov 2026 07:24:38 -0800 (PST) X-Received: by 2002:a05:6000:4021:b0:48e:4300:c70e with SMTP id ffacd0b85a97d-48e6e304059mr28974578f8f.46.1793719478219; Tue, 03 Nov 2026 07:24:38 -0800 (PST) Received: from localhost ([213.175.37.14]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e7a1d9d71sm20300171f8f.48.2026.11.03.07.24.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Nov 2026 07:24:37 -0800 (PST) X-Archived-By: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 03 Nov 2026 16:24:36 +0100 Message-Id: Cc: , , , , , , , , , , Subject: Re: [PATCH 2/2] tests/qtest/usb-hcd-ehci: test descriptor reads that fail From: "Tommaso Califano" To: "Junjie Cao" , X-Mailer: aerc 0.22.0 References: <20261103123350.1253202-1-junjie.cao@linux.dev> <20261103123350.1253202-3-junjie.cao@linux.dev> In-Reply-To: <20261103123350.1253202-3-junjie.cao@linux.dev> Received-SPF: pass client-ip=170.10.133.124; envelope-from=tcalifano@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Tue Nov 3, 2026 at 1:33 PM CET, Junjie Cao wrote: > Run the async schedule into an unreadable list head, into a head QH > whose horizontal link is unreadable and into a QH whose next qTD is > unreadable, and the periodic schedule into an unreadable siTD. Each > must raise HSE, clear Run/Stop and leave the controller halted with > both schedules idle on the following frames; before the previous patch > QEMU aborted there. A reset afterwards must bring the controller back. > > Signed-off-by: Junjie Cao I'm not very familiar with qtest, but this LGTM. Reviewed-by: Tommaso Califano Regards, Tommaso > --- > tests/qtest/usb-hcd-ehci-test.c | 119 ++++++++++++++++++++++++++++++++ > 1 file changed, 119 insertions(+) > > diff --git a/tests/qtest/usb-hcd-ehci-test.c b/tests/qtest/usb-hcd-ehci-t= est.c > index 87e37cdd7c..b0a0b6df9b 100644 > --- a/tests/qtest/usb-hcd-ehci-test.c > +++ b/tests/qtest/usb-hcd-ehci-test.c > @@ -12,6 +12,7 @@ > #include "libqos/pci-pc.h" > #include "hw/usb/uhci-regs.h" > #include "hw/usb/ehci-regs.h" > +#include "hw/usb/hcd-ehci.h" > #include "libqos/usb.h" > =20 > static QPCIBus *pcibus; > @@ -142,6 +143,123 @@ static void pci_ehci_port_hotplug(void) > usb_test_hotplug(global_qtest, "ich9-ehci-1", "3", pci_ehci_port_3_h= otplug); > } > =20 > +/* operational registers, relative to the BAR */ > +#define EHCI_USBCMD 0x20 > +#define EHCI_USBSTS 0x24 > +#define EHCI_PERIODICLISTBASE 0x34 > +#define EHCI_ASYNCLISTADDR 0x38 > + > +#define NLPTR_TYPE_QH (1 << 1) > +#define NLPTR_TYPE_SITD (2 << 1) > +#define NLPTR_T 1 > + > +#define QH_ADDR 0x100000 /* in the default 128 MiB of= RAM */ > +#define FRAME_LIST_ADDR 0x101000 > +#define BAD_ADDR 0x40000000 /* above RAM, nothing mapped= */ > +#define FRAME_NS 1000000 > + > +static uint32_t ehci_readl(uint32_t off) > +{ > + return qpci_io_readl(ehci1.dev, ehci1.bar, off); > +} > + > +static void ehci_writel(uint32_t off, uint32_t val) > +{ > + qpci_io_writel(ehci1.dev, ehci1.bar, off, val); > +} > + > +static void ehci_hcreset(void) > +{ > + ehci_writel(EHCI_USBCMD, USBCMD_HCRESET); > + g_assert_cmphex(ehci_readl(EHCI_USBCMD) & USBCMD_HCRESET, =3D=3D, 0)= ; > + g_assert_cmphex(ehci_readl(EHCI_USBSTS) & USBSTS_HALT, =3D=3D, USBST= S_HALT); > +} > + > +static void ehci_write_qh(uint32_t next, uint32_t next_qtd) > +{ > + uint32_t qh[16] =3D { > + next, > + QH_EPCHAR_H | (64 << QH_EPCHAR_MPLEN_SH) | > + (EHCI_QH_EPS_HIGH << QH_EPCHAR_EPS_SH), > + 1 << QH_EPCAP_MULT_SH, > + 0, /* current qTD */ > + next_qtd, > + NLPTR_T, /* alternate next qTD */ > + 0, /* token: inactive */ > + }; > + > + memwrite(QH_ADDR, qh, sizeof(qh)); > +} > + > +/* Run a schedule into a descriptor that cannot be read. */ > +static void ehci_run_into_dma_error(uint32_t usbcmd) > +{ > + uint32_t sts; > + int i; > + > + ehci_writel(EHCI_USBCMD, usbcmd); > + for (i =3D 0; i < 16; i++) { > + clock_step(FRAME_NS); > + if (ehci_readl(EHCI_USBSTS) & USBSTS_HSE) { > + break; > + } > + } > + g_assert_cmphex(ehci_readl(EHCI_USBSTS) & USBSTS_HSE, =3D=3D, USBSTS= _HSE); > + g_assert_cmphex(ehci_readl(EHCI_USBCMD) & USBCMD_RUNSTOP, =3D=3D, 0)= ; > + > + for (i =3D 0; i < 4; i++) { > + clock_step(FRAME_NS); > + } > + sts =3D ehci_readl(EHCI_USBSTS); > + g_assert_cmphex(sts & USBSTS_HALT, =3D=3D, USBSTS_HALT); > + g_assert_cmphex(sts & (USBSTS_ASS | USBSTS_PSS), =3D=3D, 0); > + > + /* a reset must bring the controller back */ > + ehci_hcreset(); > + ehci_write_qh(QH_ADDR | NLPTR_TYPE_QH, NLPTR_T); > + ehci_writel(EHCI_ASYNCLISTADDR, QH_ADDR); > + ehci_writel(EHCI_USBCMD, USBCMD_RUNSTOP | USBCMD_ASE); > + for (i =3D 0; i < 4; i++) { > + clock_step(FRAME_NS); > + } > + g_assert_cmphex(ehci_readl(EHCI_USBSTS) & (USBSTS_HSE | USBSTS_HALT)= , > + =3D=3D, 0); > + g_assert_cmphex(ehci_readl(EHCI_USBCMD) & USBCMD_RUNSTOP, =3D=3D, > + USBCMD_RUNSTOP); > + ehci_hcreset(); > +} > + > +static void pci_ehci_dma_error(void) > +{ > + uint32_t entries[32]; > + int i; > + > + g_assert(pcibus !=3D NULL); > + ehci_hcreset(); > + > + /* async schedule: the list head itself is unreadable */ > + ehci_writel(EHCI_ASYNCLISTADDR, BAD_ADDR); > + ehci_run_into_dma_error(USBCMD_RUNSTOP | USBCMD_ASE); > + > + /* async schedule: the head QH links to an unreadable QH */ > + ehci_write_qh(BAD_ADDR | NLPTR_TYPE_QH, NLPTR_T); > + ehci_writel(EHCI_ASYNCLISTADDR, QH_ADDR); > + ehci_run_into_dma_error(USBCMD_RUNSTOP | USBCMD_ASE); > + > + /* async schedule: a readable QH points at an unreadable qTD */ > + ehci_write_qh(QH_ADDR | NLPTR_TYPE_QH, BAD_ADDR); > + ehci_writel(EHCI_ASYNCLISTADDR, QH_ADDR); > + ehci_run_into_dma_error(USBCMD_RUNSTOP | USBCMD_ASE); > + > + /* periodic schedule: the frame list points at an unreadable siTD */ > + for (i =3D 0; i < ARRAY_SIZE(entries); i++) { > + entries[i] =3D BAD_ADDR | NLPTR_TYPE_SITD; > + } > + memwrite(FRAME_LIST_ADDR, entries, sizeof(entries)); > + ehci_writel(EHCI_PERIODICLISTBASE, FRAME_LIST_ADDR); > + ehci_run_into_dma_error(USBCMD_RUNSTOP | USBCMD_PSE); > +} > + > =20 > int main(int argc, char **argv) > { > @@ -160,6 +278,7 @@ int main(int argc, char **argv) > qtest_add_func("/ehci/pci/uhci-port-2", pci_uhci_port_2); > qtest_add_func("/ehci/pci/ehci-port-2", pci_ehci_port_2); > qtest_add_func("/ehci/pci/ehci-port-3-hotplug", pci_ehci_port_hotplu= g); > + qtest_add_func("/ehci/pci/ehci-dma-error", pci_ehci_dma_error); > =20 > qtest_start("-machine q35 -device ich9-usb-ehci1,bus=3Dpcie.0,addr= =3D1d.7," > "multifunction=3Don,id=3Dich9-ehci-1 "