[U-Boot-Users] Format of MMUCSR0 on 8540

[Charles J Gillan <C.Gillan@ecit.qub.ac.uk>]

I downloaded U-boot from CVS on Nov 14th and have compiled
and run this on a TQM8540 board (with a Rev 2 MPC8540 chip).

However, I started stepping through this with the CodeWarrior
debugger (and a FreeScale USB TAP - COP version) find that 
the "isync" in the 
following code from start.S is actually causing Interrupt 14 
to be executed (TLBInstructionException).

	/*
	 * Invalidate MMU L1/L2
	 *
	 * Note: There is a fixup earlier for Errata CPU4 on
	 * Rev 1 parts that must precede this MMU invalidation.
	 */
	li	r2, 0x001e
	mtspr	MMUCSR0, r2
	isync  <------------------- Interrupt

Without CodeWarrior, I do eventually see the U-Boot command
line appear on the serial port (however it did take several seconds
after power on, more than I expected).

Checking the 8540RM manual, I see that there appear to be only two 
bits that need to be set to invalidate cache (page 633 on MMUCSR0).

Can anyone on the explain the presence of 

       0x001e

as opposed to 

       0x0006 

in the above code?

Any suggestions as to why this exception arises. Has anyone seen it with 
An Abatron BDI2000 or not - as the case may be.

Thanks,

Charles.

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Dr Charles J Gillan
The Institute of Electronics, Communications and 
       Information Technology (ECIT),???????????????
Queen's University Belfast, Titanic Quarter
Queen?s Road, Queen?s Island, Belfast, BT3 9DT
Northern Ireland, UK
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Tel:  +44 (0) 2890 971847
Fax: +44 (0) 2890 971702
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