[U-Boot-Users] Format of MMUCSR0 on 8540

[U-Boot-Users] Format of MMUCSR0 on 8540

[Charles J Gillan]

I downloaded U-boot from CVS on Nov 14th and have compiled
and run this on a TQM8540 board (with a Rev 2 MPC8540 chip).

However, I started stepping through this with the CodeWarrior
debugger (and a FreeScale USB TAP - COP version) find that 
the "isync" in the 
following code from start.S is actually causing Interrupt 14 
to be executed (TLBInstructionException).

	/*
	 * Invalidate MMU L1/L2
	 *
	 * Note: There is a fixup earlier for Errata CPU4 on
	 * Rev 1 parts that must precede this MMU invalidation.
	 */
	li	r2, 0x001e
	mtspr	MMUCSR0, r2
	isync  <------------------- Interrupt

Without CodeWarrior, I do eventually see the U-Boot command
line appear on the serial port (however it did take several seconds
after power on, more than I expected).

Checking the 8540RM manual, I see that there appear to be only two 
bits that need to be set to invalidate cache (page 633 on MMUCSR0).

Can anyone on the explain the presence of 

       0x001e

as opposed to 

       0x0006 

in the above code?

Any suggestions as to why this exception arises. Has anyone seen it with 
An Abatron BDI2000 or not - as the case may be.

Thanks,

Charles.

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Dr Charles J Gillan
The Institute of Electronics, Communications and 
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Queen's University Belfast, Titanic Quarter
Queen?s Road, Queen?s Island, Belfast, BT3 9DT
Northern Ireland, UK
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Tel:  +44 (0) 2890 971847
Fax: +44 (0) 2890 971702
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[U-Boot-Users] Format of MMUCSR0 on 8540

[Kumar Gala]

On Nov 18, 2005, at 9:19 AM, Charles J Gillan wrote:

>
> I downloaded U-boot from CVS on Nov 14th and have compiled
> and run this on a TQM8540 board (with a Rev 2 MPC8540 chip).
>
> However, I started stepping through this with the CodeWarrior
> debugger (and a FreeScale USB TAP - COP version) find that
> the "isync" in the
> following code from start.S is actually causing Interrupt 14
> to be executed (TLBInstructionException).
>
> 	/*
> 	 * Invalidate MMU L1/L2
> 	 *
> 	 * Note: There is a fixup earlier for Errata CPU4 on
> 	 * Rev 1 parts that must precede this MMU invalidation.
> 	 */
> 	li	r2, 0x001e
> 	mtspr	MMUCSR0, r2
> 	isync  <------------------- Interrupt
>
> Without CodeWarrior, I do eventually see the U-Boot command
> line appear on the serial port (however it did take several seconds
> after power on, more than I expected).
>
> Checking the 8540RM manual, I see that there appear to be only two
> bits that need to be set to invalidate cache (page 633 on MMUCSR0).
>
> Can anyone on the explain the presence of
>
>        0x001e
>
> as opposed to
>
>        0x0006
>
> in the above code?

It's flash invalidating ALL of the TLB arrays.  A value of 0x6 will  
only do the L2 arrays.

> Any suggestions as to why this exception arises. Has anyone seen it  
> with
> An Abatron BDI2000 or not - as the case may be.

Can you see what's in the following registers, ESR, SRR0, SRR1?

Also, if I remember correctly there are some patches to u-boot for it  
to work properly with the CodeWarrior JTAG debuggers.

- kumar

[U-Boot-Users] Format of MMUCSR0 on 8540

[Charles J Gillan]

Thanks Kumar, for the information.

	> Can you see what's in the following registers, ESR, SRR0, SRR1?

      I stopped the code at the interrupt handler and see the following:

	ESR  = 0x00000000
      SRR0 = 0xFFFC0E00  (the address set in IVOR14 was 0x0e00,
                          TEXT_BASE = FFFC0000) 
      SRR1 = 0x00000200   

      There is no information on page 6-18 of the 8540RM where these
      registers are defined. Does the SRR1 value have significance?

	> Also, if I remember correctly there are some patches to u-boot for

      > it to work properly with the CodeWarrior JTAG debuggers.

      From where would I get these? Only FreeScale/Metrowerks ?

Charles.

-----Original Message-----
From: Kumar Gala [mailto:galak at kernel.crashing.org] 
Sent: 18 November 2005 15:43
To: C.Gillan at ecit.qub.ac.uk
Cc: u-boot-users at lists.sourceforge.net
Subject: Re: [U-Boot-Users] Format of MMUCSR0 on 8540


On Nov 18, 2005, at 9:19 AM, Charles J Gillan wrote:

>
> I downloaded U-boot from CVS on Nov 14th and have compiled
> and run this on a TQM8540 board (with a Rev 2 MPC8540 chip).
>
> However, I started stepping through this with the CodeWarrior
> debugger (and a FreeScale USB TAP - COP version) find that
> the "isync" in the
> following code from start.S is actually causing Interrupt 14
> to be executed (TLBInstructionException).
>
> 	/*
> 	 * Invalidate MMU L1/L2
> 	 *
> 	 * Note: There is a fixup earlier for Errata CPU4 on
> 	 * Rev 1 parts that must precede this MMU invalidation.
> 	 */
> 	li	r2, 0x001e
> 	mtspr	MMUCSR0, r2
> 	isync  <------------------- Interrupt
>
> Without CodeWarrior, I do eventually see the U-Boot command
> line appear on the serial port (however it did take several seconds
> after power on, more than I expected).
>
> Checking the 8540RM manual, I see that there appear to be only two
> bits that need to be set to invalidate cache (page 633 on MMUCSR0).
>
> Can anyone on the explain the presence of
>
>        0x001e
>
> as opposed to
>
>        0x0006
>
> in the above code?

It's flash invalidating ALL of the TLB arrays.  A value of 0x6 will  
only do the L2 arrays.

> Any suggestions as to why this exception arises. Has anyone seen it  
> with
> An Abatron BDI2000 or not - as the case may be.

Can you see what's in the following registers, ESR, SRR0, SRR1?

Also, if I remember correctly there are some patches to u-boot for it  
to work properly with the CodeWarrior JTAG debuggers.

- kumar

[U-Boot-Users] Format of MMUCSR0 on 8540

[Kumar Gala]

On Nov 18, 2005, at 10:19 AM, Charles J Gillan wrote:

>
>
> Thanks Kumar, for the information.
>
> 	> Can you see what's in the following registers, ESR, SRR0, SRR1?
>
>       I stopped the code at the interrupt handler and see the  
> following:
>
> 	ESR  = 0x00000000
>       SRR0 = 0xFFFC0E00  (the address set in IVOR14 was 0x0e00,
>                           TEXT_BASE = FFFC0000)
>       SRR1 = 0x00000200
>
>       There is no information on page 6-18 of the 8540RM where these
>       registers are defined. Does the SRR1 value have significance?

You need the e500 Core UM for these and all CPU registers.  These  
regs are the exception save/restore registers.  SRR0 is the address  
of the instruction that faulted and SRR1 is the MSR when the fault  
occurred.

Are you able to dump the TLBs out with the debugger you have?  If so  
that would be useful.

> 	> Also, if I remember correctly there are some patches to u-boot for
>
>> it to work properly with the CodeWarrior JTAG debuggers.
>
>       From where would I get these? Only FreeScale/Metrowerks ?

Yeah.  You'll have to get it from Freescale/Metrowerks.  If you  
download the Freescale Linux "BSP" for 8540 it should have the patches.

- kumar

> -----Original Message-----
> From: Kumar Gala [mailto:galak at kernel.crashing.org]
> Sent: 18 November 2005 15:43
> To: C.Gillan at ecit.qub.ac.uk
> Cc: u-boot-users at lists.sourceforge.net
> Subject: Re: [U-Boot-Users] Format of MMUCSR0 on 8540
>
>
> On Nov 18, 2005, at 9:19 AM, Charles J Gillan wrote:
>
>>
>> I downloaded U-boot from CVS on Nov 14th and have compiled
>> and run this on a TQM8540 board (with a Rev 2 MPC8540 chip).
>>
>> However, I started stepping through this with the CodeWarrior
>> debugger (and a FreeScale USB TAP - COP version) find that
>> the "isync" in the
>> following code from start.S is actually causing Interrupt 14
>> to be executed (TLBInstructionException).
>>
>> 	/*
>> 	 * Invalidate MMU L1/L2
>> 	 *
>> 	 * Note: There is a fixup earlier for Errata CPU4 on
>> 	 * Rev 1 parts that must precede this MMU invalidation.
>> 	 */
>> 	li	r2, 0x001e
>> 	mtspr	MMUCSR0, r2
>> 	isync  <------------------- Interrupt
>>
>> Without CodeWarrior, I do eventually see the U-Boot command
>> line appear on the serial port (however it did take several seconds
>> after power on, more than I expected).
>>
>> Checking the 8540RM manual, I see that there appear to be only two
>> bits that need to be set to invalidate cache (page 633 on MMUCSR0).
>>
>> Can anyone on the explain the presence of
>>
>>        0x001e
>>
>> as opposed to
>>
>>        0x0006
>>
>> in the above code?
>
> It's flash invalidating ALL of the TLB arrays.  A value of 0x6 will
> only do the L2 arrays.
>
>> Any suggestions as to why this exception arises. Has anyone seen it
>> with
>> An Abatron BDI2000 or not - as the case may be.
>
> Can you see what's in the following registers, ESR, SRR0, SRR1?
>
> Also, if I remember correctly there are some patches to u-boot for it
> to work properly with the CodeWarrior JTAG debuggers.
>
> - kumar
>
>
>
>
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[U-Boot-Users] Format of MMUCSR0 on 8540

[Wolfgang Denk]

In message <977AA505-6DBA-4F85-ACB8-37B452CF9417@kernel.crashing.org> you wrote:
> 
> >       From where would I get these? Only FreeScale/Metrowerks ?
> 
> Yeah.  You'll have to get it from Freescale/Metrowerks.  If you  

Why doesn't Freescale post this stuff here on the list?

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Why waste negative entropy on comments, when you could use the  same
entropy to create bugs instead?"                        - Steve Elias

[U-Boot-Users] Format of MMUCSR0 on 8540

[Kumar Gala]

On Nov 18, 2005, at 2:11 PM, Wolfgang Denk wrote:

> In message <977AA505-6DBA-4F85- 
> ACB8-37B452CF9417 at kernel.crashing.org> you wrote:
>>
>>>       From where would I get these? Only FreeScale/Metrowerks ?
>>
>> Yeah.  You'll have to get it from Freescale/Metrowerks.  If you
>
> Why doesn't Freescale post this stuff here on the list?

You would have to ask Freescale that :)

Ron, Neil you guys around??

- kumar