All of lore.kernel.org
 help / color / mirror / Atom feed
From: Blue Swirl <blauwirbel@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [4405] Fix compiler warnings in common files
Date: Sat, 10 May 2008 10:14:23 +0000	[thread overview]
Message-ID: <E1Jum5v-0003CV-JS@cvs.savannah.gnu.org> (raw)

Revision: 4405
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4405
Author:   blueswir1
Date:     2008-05-10 10:14:22 +0000 (Sat, 10 May 2008)

Log Message:
-----------
Fix compiler warnings in common files

Modified Paths:
--------------
    trunk/cpu-all.h
    trunk/cpu-exec.c
    trunk/dis-asm.h
    trunk/exec-all.h
    trunk/softmmu_header.h
    trunk/sysemu.h

Modified: trunk/cpu-all.h
===================================================================
--- trunk/cpu-all.h	2008-05-10 10:12:00 UTC (rev 4404)
+++ trunk/cpu-all.h	2008-05-10 10:14:22 UTC (rev 4405)
@@ -452,7 +452,7 @@
 {
     uint32_t a,b;
     a = ldl_be_p(ptr);
-    b = ldl_be_p(ptr+4);
+    b = ldl_be_p((uint8_t *)ptr + 4);
     return (((uint64_t)a<<32)|b);
 }
 
@@ -489,7 +489,7 @@
 static inline void stq_be_p(void *ptr, uint64_t v)
 {
     stl_be_p(ptr, v >> 32);
-    stl_be_p(ptr + 4, v);
+    stl_be_p((uint8_t *)ptr + 4, v);
 }
 
 /* float access */
@@ -518,7 +518,7 @@
 {
     CPU_DoubleU u;
     u.l.upper = ldl_be_p(ptr);
-    u.l.lower = ldl_be_p(ptr + 4);
+    u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
     return u.d;
 }
 
@@ -527,7 +527,7 @@
     CPU_DoubleU u;
     u.d = v;
     stl_be_p(ptr, u.l.upper);
-    stl_be_p(ptr + 4, u.l.lower);
+    stl_be_p((uint8_t *)ptr + 4, u.l.lower);
 }
 
 #else

Modified: trunk/cpu-exec.c
===================================================================
--- trunk/cpu-exec.c	2008-05-10 10:12:00 UTC (rev 4404)
+++ trunk/cpu-exec.c	2008-05-10 10:14:22 UTC (rev 4405)
@@ -640,7 +640,7 @@
                    jump. */
                 {
                     if (next_tb != 0 &&
-#if USE_KQEMU
+#ifdef USE_KQEMU
                         (env->kqemu_enabled != 2) &&
 #endif
                         tb->page_addr[1] == -1) {

Modified: trunk/dis-asm.h
===================================================================
--- trunk/dis-asm.h	2008-05-10 10:12:00 UTC (rev 4404)
+++ trunk/dis-asm.h	2008-05-10 10:14:22 UTC (rev 4405)
@@ -396,7 +396,6 @@
 extern int print_insn_v850		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_tic30		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_ppc		PARAMS ((bfd_vma, disassemble_info*));
-extern int print_insn_alpha             PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_s390		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_crisv32           PARAMS ((bfd_vma, disassemble_info*));
 

Modified: trunk/exec-all.h
===================================================================
--- trunk/exec-all.h	2008-05-10 10:12:00 UTC (rev 4404)
+++ trunk/exec-all.h	2008-05-10 10:14:22 UTC (rev 4405)
@@ -93,13 +93,13 @@
 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
                       target_phys_addr_t paddr, int prot,
                       int mmu_idx, int is_softmmu);
-static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
+static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
                                target_phys_addr_t paddr, int prot,
                                int mmu_idx, int is_softmmu)
 {
     if (prot & PAGE_READ)
         prot |= PAGE_EXEC;
-    return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
+    return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
 }
 
 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
@@ -550,7 +550,7 @@
 #endif
 
 #if defined(CONFIG_USER_ONLY)
-static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
+static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 {
     return addr;
 }
@@ -558,25 +558,25 @@
 /* NOTE: this function can trigger an exception */
 /* NOTE2: the returned address is not exactly the physical address: it
    is the offset relative to phys_ram_base */
-static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
+static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 {
-    int mmu_idx, index, pd;
+    int mmu_idx, page_index, pd;
 
-    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
-    mmu_idx = cpu_mmu_index(env);
-    if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
+    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+    mmu_idx = cpu_mmu_index(env1);
+    if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code !=
                          (addr & TARGET_PAGE_MASK), 0)) {
         ldub_code(addr);
     }
-    pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
+    pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
         do_unassigned_access(addr, 0, 1, 0);
 #else
-        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
+        cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 #endif
     }
-    return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
+    return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
 }
 #endif
 

Modified: trunk/softmmu_header.h
===================================================================
--- trunk/softmmu_header.h	2008-05-10 10:12:00 UTC (rev 4404)
+++ trunk/softmmu_header.h	2008-05-10 10:14:22 UTC (rev 4405)
@@ -222,20 +222,20 @@
 
 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
 {
-    int index;
+    int page_index;
     RES_TYPE res;
     target_ulong addr;
     unsigned long physaddr;
     int mmu_idx;
 
     addr = ptr;
-    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
     mmu_idx = CPU_MMU_INDEX;
-    if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
+    if (__builtin_expect(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
         res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
     } else {
-        physaddr = addr + env->tlb_table[mmu_idx][index].addend;
+        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
         res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
     }
     return res;
@@ -244,19 +244,19 @@
 #if DATA_SIZE <= 2
 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
 {
-    int res, index;
+    int res, page_index;
     target_ulong addr;
     unsigned long physaddr;
     int mmu_idx;
 
     addr = ptr;
-    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
     mmu_idx = CPU_MMU_INDEX;
-    if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
+    if (__builtin_expect(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
         res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
     } else {
-        physaddr = addr + env->tlb_table[mmu_idx][index].addend;
+        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
         res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
     }
     return res;
@@ -269,19 +269,19 @@
 
 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
 {
-    int index;
+    int page_index;
     target_ulong addr;
     unsigned long physaddr;
     int mmu_idx;
 
     addr = ptr;
-    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
     mmu_idx = CPU_MMU_INDEX;
-    if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_write !=
+    if (__builtin_expect(env->tlb_table[mmu_idx][page_index].addr_write !=
                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
         glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
     } else {
-        physaddr = addr + env->tlb_table[mmu_idx][index].addend;
+        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
         glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
     }
 }

Modified: trunk/sysemu.h
===================================================================
--- trunk/sysemu.h	2008-05-10 10:12:00 UTC (rev 4404)
+++ trunk/sysemu.h	2008-05-10 10:14:22 UTC (rev 4405)
@@ -130,8 +130,8 @@
 #define MAX_SCSI_DEVS	7
 #define MAX_DRIVES 32
 
-int nb_drives;
-DriveInfo drives_table[MAX_DRIVES+1];
+extern int nb_drives;
+extern DriveInfo drives_table[MAX_DRIVES+1];
 
 extern int drive_get_index(BlockInterfaceType type, int bus, int unit);
 extern int drive_get_max_bus(BlockInterfaceType type);

                 reply	other threads:[~2008-05-10 10:14 UTC|newest]

Thread overview: [no followups] expand[flat|nested]  mbox.gz  Atom feed

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=E1Jum5v-0003CV-JS@cvs.savannah.gnu.org \
    --to=blauwirbel@gmail.com \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.