From: Andrzej Zaborowski <balrogg@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [4899] ARM: fix CPS masks (Vincent Palatin).
Date: Sat, 19 Jul 2008 10:34:36 +0000 [thread overview]
Message-ID: <E1KK9ls-0002Li-9L@cvs.savannah.gnu.org> (raw)
Revision: 4899
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4899
Author: balrog
Date: 2008-07-19 10:34:35 +0000 (Sat, 19 Jul 2008)
Log Message:
-----------
ARM: fix CPS masks (Vincent Palatin).
According to ARM Reference Manual (DDI0100 A4.1.16),
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
should be 0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)
Modified Paths:
--------------
trunk/target-arm/translate.c
Modified: trunk/target-arm/translate.c
===================================================================
--- trunk/target-arm/translate.c 2008-07-19 10:12:22 UTC (rev 4898)
+++ trunk/target-arm/translate.c 2008-07-19 10:34:35 UTC (rev 4899)
@@ -5813,7 +5813,7 @@
/* Coprocessor double register transfer. */
} else if ((insn & 0x0f000010) == 0x0e000010) {
/* Additional coprocessor register transfer. */
- } else if ((insn & 0x0ff10010) == 0x01000000) {
+ } else if ((insn & 0x0ff10020) == 0x01000000) {
uint32_t mask;
uint32_t val;
/* cps (privileged) */
@@ -5830,7 +5830,7 @@
if (insn & (1 << 18))
val |= mask;
}
- if (insn & (1 << 14)) {
+ if (insn & (1 << 17)) {
mask |= CPSR_M;
val |= (insn & 0x1f);
}
reply other threads:[~2008-07-19 10:34 UTC|newest]
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