From: Filip Navara <filip.navara@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 13/18] Convert disas_neon_ls_insn not to use cpu_T.
Date: Sun, 19 Jul 2009 15:20:03 -0000 [thread overview]
Message-ID: <E1MSYBG-0001OC-N6@lists.gnu.org> (raw)
Signed-off-by: Filip Navara <filip.navara@gmail.com>
---
target-arm/translate.c | 69 ++++++++++++++++++++++++-----------------------
1 files changed, 35 insertions(+), 34 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index fc40d5e..6a57918 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -3767,6 +3767,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
int load;
int shift;
int n;
+ TCGv addr;
TCGv tmp;
TCGv tmp2;
@@ -3776,6 +3777,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
rn = (insn >> 16) & 0xf;
rm = insn & 0xf;
load = (insn & (1 << 21)) != 0;
+ addr = new_tmp();
if ((insn & (1 << 23)) == 0) {
/* Load store all elements. */
op = (insn >> 8) & 0xf;
@@ -3784,32 +3786,30 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
return 1;
nregs = neon_ls_element_type[op].nregs;
interleave = neon_ls_element_type[op].interleave;
- gen_movl_T1_reg(s, rn);
+ tcg_gen_mov_i32(addr, cpu_R[rn]);
stride = (1 << size) * interleave;
for (reg = 0; reg < nregs; reg++) {
if (interleave > 2 || (interleave == 2 && nregs == 2)) {
- gen_movl_T1_reg(s, rn);
- gen_op_addl_T1_im((1 << size) * reg);
+ tcg_gen_add_i32(addr, cpu_R[rn], (1 << size) * reg);
} else if (interleave == 2 && nregs == 4 && reg == 2) {
- gen_movl_T1_reg(s, rn);
- gen_op_addl_T1_im(1 << size);
+ tcg_gen_add_i32(addr, cpu_R[rn], 1 << size);
}
for (pass = 0; pass < 2; pass++) {
if (size == 2) {
if (load) {
- tmp = gen_ld32(cpu_T[1], IS_USER(s));
+ tmp = gen_ld32(addr, IS_USER(s));
neon_store_reg(rd, pass, tmp);
} else {
tmp = neon_load_reg(rd, pass);
- gen_st32(tmp, cpu_T[1], IS_USER(s));
+ gen_st32(tmp, addr, IS_USER(s));
}
- gen_op_addl_T1_im(stride);
+ tcg_gen_addi_i32(addr, addr, stride);
} else if (size == 1) {
if (load) {
- tmp = gen_ld16u(cpu_T[1], IS_USER(s));
- gen_op_addl_T1_im(stride);
- tmp2 = gen_ld16u(cpu_T[1], IS_USER(s));
- gen_op_addl_T1_im(stride);
+ tmp = gen_ld16u(addr, IS_USER(s));
+ tcg_gen_addi_i32(addr, addr, stride);
+ tmp2 = gen_ld16u(addr, IS_USER(s));
+ tcg_gen_addi_i32(addr, addr, stride);
gen_bfi(tmp, tmp, tmp2, 16, 0xffff);
dead_tmp(tmp2);
neon_store_reg(rd, pass, tmp);
@@ -3817,17 +3817,17 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
tmp = neon_load_reg(rd, pass);
tmp2 = new_tmp();
tcg_gen_shri_i32(tmp2, tmp, 16);
- gen_st16(tmp, cpu_T[1], IS_USER(s));
- gen_op_addl_T1_im(stride);
- gen_st16(tmp2, cpu_T[1], IS_USER(s));
- gen_op_addl_T1_im(stride);
+ gen_st16(tmp, addr, IS_USER(s));
+ tcg_gen_addi_i32(addr, addr, stride);
+ gen_st16(tmp2, addr, IS_USER(s));
+ tcg_gen_addi_i32(addr, addr, stride);
}
} else /* size == 0 */ {
if (load) {
TCGV_UNUSED(tmp2);
for (n = 0; n < 4; n++) {
- tmp = gen_ld8u(cpu_T[1], IS_USER(s));
- gen_op_addl_T1_im(stride);
+ tmp = gen_ld8u(addr, IS_USER(s));
+ tcg_gen_addi_i32(addr, addr, stride);
if (n == 0) {
tmp2 = tmp;
} else {
@@ -3845,8 +3845,8 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
} else {
tcg_gen_shri_i32(tmp, tmp2, n * 8);
}
- gen_st8(tmp, cpu_T[1], IS_USER(s));
- gen_op_addl_T1_im(stride);
+ gen_st8(tmp, addr, IS_USER(s));
+ tcg_gen_addi_i32(addr, addr, stride);
}
dead_tmp(tmp2);
}
@@ -3854,7 +3854,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
}
rd += neon_ls_element_type[op].spacing;
}
- stride = nregs * 8;
+ stride = nregs * 8;
} else {
size = (insn >> 10) & 3;
if (size == 3) {
@@ -3864,26 +3864,26 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
size = (insn >> 6) & 3;
nregs = ((insn >> 8) & 3) + 1;
stride = (insn & (1 << 5)) ? 2 : 1;
- gen_movl_T1_reg(s, rn);
+ tcg_gen_mov_i32(addr, cpu_R[rn]);
for (reg = 0; reg < nregs; reg++) {
switch (size) {
case 0:
- tmp = gen_ld8u(cpu_T[1], IS_USER(s));
+ tmp = gen_ld8u(addr, IS_USER(s));
gen_neon_dup_u8(tmp, 0);
break;
case 1:
- tmp = gen_ld16u(cpu_T[1], IS_USER(s));
+ tmp = gen_ld16u(addr, IS_USER(s));
gen_neon_dup_low16(tmp);
break;
case 2:
- tmp = gen_ld32(cpu_T[0], IS_USER(s));
+ tmp = gen_ld32(addr, IS_USER(s));
break;
case 3:
return 1;
default: /* Avoid compiler warnings. */
abort();
}
- gen_op_addl_T1_im(1 << size);
+ tcg_gen_addi_i32(addr, addr, 1 << size);
tmp2 = new_tmp();
tcg_gen_mov_i32(tmp2, tmp);
neon_store_reg(rd, 0, tmp2);
@@ -3911,18 +3911,18 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
abort();
}
nregs = ((insn >> 8) & 3) + 1;
- gen_movl_T1_reg(s, rn);
+ tcg_gen_mov_i32(addr, cpu_R[rn]);
for (reg = 0; reg < nregs; reg++) {
if (load) {
switch (size) {
case 0:
- tmp = gen_ld8u(cpu_T[1], IS_USER(s));
+ tmp = gen_ld8u(addr, IS_USER(s));
break;
case 1:
- tmp = gen_ld16u(cpu_T[1], IS_USER(s));
+ tmp = gen_ld16u(addr, IS_USER(s));
break;
case 2:
- tmp = gen_ld32(cpu_T[1], IS_USER(s));
+ tmp = gen_ld32(addr, IS_USER(s));
break;
default: /* Avoid compiler warnings. */
abort();
@@ -3939,22 +3939,23 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
tcg_gen_shri_i32(tmp, tmp, shift);
switch (size) {
case 0:
- gen_st8(tmp, cpu_T[1], IS_USER(s));
+ gen_st8(tmp, addr, IS_USER(s));
break;
case 1:
- gen_st16(tmp, cpu_T[1], IS_USER(s));
+ gen_st16(tmp, addr, IS_USER(s));
break;
case 2:
- gen_st32(tmp, cpu_T[1], IS_USER(s));
+ gen_st32(tmp, addr, IS_USER(s));
break;
}
}
rd += stride;
- gen_op_addl_T1_im(1 << size);
+ tcg_gen_addi_i32(addr, addr, 1 << size);
}
stride = nregs * (1 << size);
}
}
+ dead_tmp(addr);
if (rm != 15) {
TCGv base;
--
1.6.3.2.1299.gee46c
next reply other threads:[~2009-07-19 15:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-07-19 15:20 Filip Navara [this message]
2009-10-15 18:35 ` [Qemu-devel] [PATCH 13/18] Convert disas_neon_ls_insn not to use cpu_T Aurelien Jarno
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