From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 05/23] ARM: entry: abort-macro: specify registers to be used for macros
Date: Wed, 29 Jun 2011 10:20:34 +0100 [thread overview]
Message-ID: <E1Qbqwk-0002F0-AF@rmk-PC.arm.linux.org.uk> (raw)
In-Reply-To: <20110629091853.GK21898@n2100.arm.linux.org.uk>
Require all callers of abort macros to specify the registers to be
used. This improves the documentation at the callsites as to which
registers are being used by this assembly code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mm/abort-ev4t.S | 2 +-
arch/arm/mm/abort-ev5t.S | 4 ++--
arch/arm/mm/abort-ev5tj.S | 4 ++--
arch/arm/mm/abort-ev6.S | 4 ++--
arch/arm/mm/abort-macro.S | 30 +++++++++++++++---------------
5 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mm/abort-ev4t.S b/arch/arm/mm/abort-ev4t.S
index b628254..9910123 100644
--- a/arch/arm/mm/abort-ev4t.S
+++ b/arch/arm/mm/abort-ev4t.S
@@ -22,7 +22,7 @@
ENTRY(v4t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
- do_thumb_abort
+ do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #1 << 20 @ check write
diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S
index 02251b5..800e8d4 100644
--- a/arch/arm/mm/abort-ev5t.S
+++ b/arch/arm/mm/abort-ev5t.S
@@ -22,10 +22,10 @@
ENTRY(v5t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
- do_thumb_abort
+ do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction
bic r1, r1, #1 << 11 @ clear bits 11 of FSR
- do_ldrd_abort
+ do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ check write
orreq r1, r1, #1 << 11
mov pc, lr
diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index bce68d6..bcb58d2 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -25,9 +25,9 @@ ENTRY(v5tj_early_abort)
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #PSR_J_BIT @ Java?
movne pc, lr
- do_thumb_abort
+ do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction
- do_ldrd_abort
+ do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
mov pc, lr
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 1478aa5..ef526e7 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -35,12 +35,12 @@ ENTRY(v6_early_abort)
bic r1, r1, #1 << 11 @ clear bit 11 of FSR
tst r3, #PSR_J_BIT @ Java?
movne pc, lr
- do_thumb_abort
+ do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction
#ifdef CONFIG_CPU_ENDIAN_BE8
reveq r3, r3
#endif
- do_ldrd_abort
+ do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
mov pc, lr
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index d7cb1bf..8d3b9f9 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -9,33 +9,33 @@
*
*/
- .macro do_thumb_abort
- tst r3, #PSR_T_BIT
+ .macro do_thumb_abort, fsr, pc, psr, tmp
+ tst \psr, #PSR_T_BIT
beq not_thumb
- ldrh r3, [r2] @ Read aborted Thumb instruction
- and r3, r3, # 0xfe00 @ Mask opcode field
- cmp r3, # 0x5600 @ Is it ldrsb?
- orreq r3, r3, #1 << 11 @ Set L-bit if yes
- tst r3, #1 << 11 @ L = 0 -> write
- orreq r1, r1, #1 << 11 @ yes.
+ ldrh \tmp, [\pc] @ Read aborted Thumb instruction
+ and \tmp, \tmp, # 0xfe00 @ Mask opcode field
+ cmp \tmp, # 0x5600 @ Is it ldrsb?
+ orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
+ tst \tmp, #1 << 11 @ L = 0 -> write
+ orreq \psr, \psr, #1 << 11 @ yes.
mov pc, lr
not_thumb:
.endm
/*
- * We check for the following insturction encoding for LDRD.
+ * We check for the following instruction encoding for LDRD.
*
- * [27:25] == 0
+ * [27:25] == 000
* [7:4] == 1101
* [20] == 0
*/
- .macro do_ldrd_abort
- tst r3, #0x0e000000 @ [27:25] == 0
+ .macro do_ldrd_abort, tmp, insn
+ tst \insn, #0x0e000000 @ [27:25] == 0
bne not_ldrd
- and r2, r3, #0x000000f0 @ [7:4] == 1101
- cmp r2, #0x000000d0
+ and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
+ cmp \tmp, #0x000000d0
bne not_ldrd
- tst r3, #1 << 20 @ [20] == 0
+ tst \insn, #1 << 20 @ [20] == 0
moveq pc, lr
not_ldrd:
.endm
--
1.7.4.4
next prev parent reply other threads:[~2011-06-29 9:20 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 01/23] ARM: entry: remove unused irq_prio_table macro Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 02/23] ARM: entry: shark: don't directly reference registers in macros Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 03/23] ARM: entry: prefetch/data abort helpers: convert to macros Russell King - ARM Linux
2011-06-29 9:20 ` [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
2011-06-29 9:20 ` [PATCH 04/23] ARM: entry: prefetch/data abort helpers: avoid corrupting r4 Russell King - ARM Linux
2011-06-29 9:20 ` Russell King - ARM Linux [this message]
2011-06-29 9:20 ` [PATCH 06/23] ARM: entry: abort-macro: simplify do_ldrd_abort Russell King - ARM Linux
2011-06-29 9:21 ` [PATCH 07/23] ARM: entry: no need to increase preempt count for IRQ handlers Russell King - ARM Linux
2011-06-29 9:21 ` [PATCH 08/23] ARM: entry: no need to check parent IRQ mask in IRQ handler return Russell King - ARM Linux
2011-06-29 9:21 ` [PATCH 09/23] ARM: entry: rejig register allocation in exception entry handlers Russell King - ARM Linux
2011-06-29 9:22 ` [PATCH 10/23] ARM: entry: prefetch abort helper: pass aborted pc in r4 rather than r0 Russell King - ARM Linux
2011-06-29 9:22 ` [PATCH 11/23] ARM: entry: avoid enabling interrupts in prefetch/data abort handlers Russell King - ARM Linux
2011-06-29 20:05 ` Will Deacon
2011-06-30 9:27 ` Russell King - ARM Linux
2011-06-30 21:51 ` Will Deacon
2011-06-29 9:22 ` [PATCH 12/23] ARM: entry: instrument svc undefined exception handler with irqtrace Russell King - ARM Linux
2011-06-29 9:23 ` [PATCH 13/23] ARM: entry: instrument usr exception handlers with irqsoff tracing Russell King - ARM Linux
2011-06-29 9:23 ` [PATCH 14/23] ARM: entry: consolidate trace_hardirqs_off into (svc|usr)_entry macros Russell King - ARM Linux
2011-06-29 9:23 ` [PATCH 15/23] ARM: entry: re-allocate registers in irq entry assembly macros Russell King - ARM Linux
2011-06-29 9:24 ` [PATCH 16/23] ARM: entry: prefetch abort: tail-call the main prefetch abort handler Russell King - ARM Linux
2011-06-29 9:24 ` [PATCH 17/23] ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5 Russell King - ARM Linux
2011-06-29 9:24 ` [PATCH 18/23] ARM: entry: data abort: avoid using r2 in abort helpers Russell King - ARM Linux
2011-06-29 9:25 ` [PATCH 19/23] ARM: entry: data abort: tail-call the main data abort handler Russell King - ARM Linux
2011-06-29 9:25 ` [PATCH 20/23] ARM: entry: data abort: use r2 as base of pt_regs rather than stack Russell King - ARM Linux
2011-06-29 9:25 ` [PATCH 21/23] ARM: entry: data abort: always use r6 for offset Russell King - ARM Linux
2011-06-29 9:26 ` [PATCH 22/23] ARM: entry: data abort: ensure r5 is preserved by abort functions Russell King - ARM Linux
2011-06-29 9:26 ` [PATCH 23/23] ARM: entry: no need to reload the SPSR value from struct pt_regs Russell King - ARM Linux
2011-06-29 14:53 ` [PATCH 00/23] entry assembly cleanups Jean-Christophe PLAGNIOL-VILLARD
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