From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
To: Andrew Lunn <andrew@lunn.ch>, Heiner Kallweit <hkallweit1@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-stm32@st-md-mailman.stormreply.com,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
netdev@vger.kernel.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Paolo Abeni <pabeni@redhat.com>
Subject: [PATCH net-next 3/4] net: stmmac: visconti: clean up code formatting
Date: Mon, 16 Jun 2025 22:06:27 +0100 [thread overview]
Message-ID: <E1uRH2B-004UyS-Ch@rmk-PC.armlinux.org.uk> (raw)
In-Reply-To: <aFCHJWXSLbUoogi6@shell.armlinux.org.uk>
Ensure that code is wrapped prior to column 80, and shorten the
needlessly long "clk_sel_val" to just "clk_sel".
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../ethernet/stmicro/stmmac/dwmac-visconti.c | 35 +++++++++++--------
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
index c2aaac4a5ac1..db82b522c248 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
@@ -57,20 +57,20 @@ static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
phy_interface_t interface, int speed)
{
struct visconti_eth *dwmac = bsp_priv;
- unsigned int val, clk_sel_val = 0;
+ unsigned int val, clk_sel = 0;
if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) {
switch (speed) {
case SPEED_1000:
- clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_125M;
+ clk_sel = ETHER_CLK_SEL_FREQ_SEL_125M;
break;
case SPEED_100:
- clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_25M;
+ clk_sel = ETHER_CLK_SEL_FREQ_SEL_25M;
break;
case SPEED_10:
- clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_2P5M;
+ clk_sel = ETHER_CLK_SEL_FREQ_SEL_2P5M;
break;
default:
@@ -79,12 +79,13 @@ static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
/* Stop internal clock */
val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL);
- val &= ~(ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN);
+ val &= ~(ETHER_CLK_SEL_RMII_CLK_EN |
+ ETHER_CLK_SEL_RX_TX_CLK_EN);
val |= ETHER_CLK_SEL_TX_O_E_N_IN;
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
/* Set Clock-Mux, Start clock, Set TX_O direction */
- val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;
+ val = clk_sel | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
@@ -95,11 +96,11 @@ static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
} else if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII) {
switch (speed) {
case SPEED_100:
- clk_sel_val = ETHER_CLK_SEL_DIV_SEL_2;
+ clk_sel = ETHER_CLK_SEL_DIV_SEL_2;
break;
case SPEED_10:
- clk_sel_val = ETHER_CLK_SEL_DIV_SEL_20;
+ clk_sel = ETHER_CLK_SEL_DIV_SEL_20;
break;
default:
@@ -108,14 +109,16 @@ static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
/* Stop internal clock */
val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL);
- val &= ~(ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN);
+ val &= ~(ETHER_CLK_SEL_RMII_CLK_EN |
+ ETHER_CLK_SEL_RX_TX_CLK_EN);
val |= ETHER_CLK_SEL_TX_O_E_N_IN;
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
/* Set Clock-Mux, Start clock, Set TX_O direction */
- val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |
- ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |
- ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;
+ val = clk_sel | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |
+ ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV |
+ ETHER_CLK_SEL_TX_O_E_N_IN |
+ ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
val |= ETHER_CLK_SEL_RMII_CLK_RST;
@@ -126,13 +129,15 @@ static int visconti_eth_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
} else {
/* Stop internal clock */
val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL);
- val &= ~(ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN);
+ val &= ~(ETHER_CLK_SEL_RMII_CLK_EN |
+ ETHER_CLK_SEL_RX_TX_CLK_EN);
val |= ETHER_CLK_SEL_TX_O_E_N_IN;
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
/* Set Clock-Mux, Start clock, Set TX_O direction */
- val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |
- ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN;
+ val = ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |
+ ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC |
+ ETHER_CLK_SEL_TX_O_E_N_IN;
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
--
2.30.2
next prev parent reply other threads:[~2025-06-16 21:15 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-16 21:05 [PATCH net-next 0/4] nte: stmmac: visconti: cleanups Russell King (Oracle)
2025-06-16 21:06 ` [PATCH net-next 1/4] net: stmmac: visconti: re-arrange speed decode Russell King (Oracle)
2025-06-16 23:29 ` Andrew Lunn
2025-06-16 21:06 ` [PATCH net-next 2/4] net: stmmac: visconti: reorganise visconti_eth_set_clk_tx_rate() Russell King (Oracle)
2025-06-16 23:34 ` Andrew Lunn
2025-06-16 21:06 ` Russell King (Oracle) [this message]
2025-06-16 23:34 ` [PATCH net-next 3/4] net: stmmac: visconti: clean up code formatting Andrew Lunn
2025-06-16 21:06 ` [PATCH net-next 4/4] net: stmmac: visconti: make phy_intf_sel local Russell King (Oracle)
2025-06-16 23:36 ` Andrew Lunn
2025-06-17 23:30 ` [PATCH net-next 0/4] nte: stmmac: visconti: cleanups patchwork-bot+netdevbpf
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