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[94.27.154.94]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255f1fb965sm96799366b.49.2026.08.28.08.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 08:37:58 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Alexander.Deucher@amd.com, Christian =?UTF-8?B?S8O2bmln?= , Natalie Vock , Marek =?UTF-8?B?T2zFocOhaw==?= , Mario Limonciello , Tvrtko Ursulin , Felix Kuehling , "Lazar, Lijo" Subject: Re: [PATCH 3/5] drm/amdgpu/sdma: Move SDMA v5.x queue reset to common code Date: Fri, 28 Aug 2026 17:37:57 +0200 Message-ID: In-Reply-To: <032550fc-5680-4f6c-974c-fe96cc8083e1@amd.com> References: <20260828120729.25908-1-timur.kristof@gmail.com> <20260828120729.25908-4-timur.kristof@gmail.com> <032550fc-5680-4f6c-974c-fe96cc8083e1@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Friday, August 28, 2026 4:20:19=E2=80=AFPM Central European Summer Time = Lazar, Lijo=20 wrote: > On 28-Aug-26 5:37 PM, Timur Krist=C3=B3f wrote: > > The code was exactly the same between SDMA v5.0 and v5.2 > > furthermore the exact same implementation can be shared > > between all SDMA versions that don't use MES. > >=20 > > Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 37 ++++++++++++++++++++++++ > > drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 4 +++ > > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 25 +--------------- > > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 25 +--------------- > > 4 files changed, 43 insertions(+), 48 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index > > 66f278f77f71..9eebd8380834 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c > > @@ -635,3 +635,40 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device > > *adev, uint32_t instance_id,>=20 > > return ret; > > =20 > > } > >=20 > > + > > +/** > > + * amdgpu_sdma_reset_queue_legacy() - Reset legacy SDMA queue after > > timeout (without MES) + * > > + * @ring: Pointer to the ring of the SDMA queue > > + * @vmid: VMID of the timed out job > > + * @timedout_fence: Fence of the timed out job > > + * > > + * Common implementation for resetting SDMA queues without MES (legacy= ). > > + * This relies on the proper amdgpu_sdma_funcs to be set up > > + * for the given ring. > > + * > > + * Applicable to SDMA versions that don't rely on the MES yet, > > + * that is all versions up to SDMA v5.x and older. > > + */ > > +int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring, > > + unsigned int vmid, > > + struct amdgpu_fence=20 *timedout_fence) > > +{ > > + struct amdgpu_device *adev =3D ring->adev; > > + int r; > > + > > + if (ring->me >=3D adev->sdma.num_instances) { > > + dev_err(adev->dev, "sdma instance not found\n"); > > + return -EINVAL; > > + } > > + > > + amdgpu_ring_reset_helper_begin(ring, timedout_fence); > > + > > + amdgpu_amdkfd_suspend(adev, true); > > + r =3D amdgpu_sdma_reset_engine(adev, ring->me, true); > > + amdgpu_amdkfd_resume(adev, true); > > + if (r) > > + return r; > > + > > + return amdgpu_ring_reset_helper_end(ring, timedout_fence); > > +} >=20 > Instead of moving it here - sdma_v5_x_reset_queue and using it for 5.2 > is better. This may not work in the same way for all legacy queues. >=20 > Thanks, > Lijo Hi, As far as I see, this function can be reused for all generations that don't= =20 use MES. If you don't think so, please explain why not. Thanks, Timur >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h index > > 4f4e56022c97..7c4e145ca0c1 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h > > @@ -160,6 +160,10 @@ struct amdgpu_buffer_funcs { > >=20 > > int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t > > instance_id,> =20 > > bool caller_handles_kernel_queues); > >=20 > > +int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring, > > + unsigned int vmid, > > + struct amdgpu_fence=20 *timedout_fence); > > + > >=20 > > #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) > > (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t)) > > #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) > > (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))>=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c > > b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 0da54c335822..76f8765fb1= 75 > > 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c > > @@ -1518,29 +1518,6 @@ static int sdma_v5_0_wait_for_idle(struct > > amdgpu_ip_block *ip_block)>=20 > > return -ETIMEDOUT; > > =20 > > } > >=20 > > -static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, > > - unsigned int vmid, > > - struct amdgpu_fence=20 *timedout_fence) > > -{ > > - struct amdgpu_device *adev =3D ring->adev; > > - int r; > > - > > - if (ring->me >=3D adev->sdma.num_instances) { > > - dev_err(adev->dev, "sdma instance not found\n"); > > - return -EINVAL; > > - } > > - > > - amdgpu_ring_reset_helper_begin(ring, timedout_fence); > > - > > - amdgpu_amdkfd_suspend(adev, true); > > - r =3D amdgpu_sdma_reset_engine(adev, ring->me, true); > > - amdgpu_amdkfd_resume(adev, true); > > - if (r) > > - return r; > > - > > - return amdgpu_ring_reset_helper_end(ring, timedout_fence); > > -} > > - > >=20 > > static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring) > > { > > =20 > > u32 f32_cntl, freeze, cntl, stat1_reg; > >=20 > > @@ -1936,7 +1913,7 @@ static const struct amdgpu_ring_funcs > > sdma_v5_0_ring_funcs =3D {>=20 > > .emit_reg_write_reg_wait =3D=20 sdma_v5_0_ring_emit_reg_write_reg_wait, > > .init_cond_exec =3D sdma_v5_0_ring_init_cond_exec, > > .preempt_ib =3D sdma_v5_0_ring_preempt_ib, > >=20 > > - .reset =3D sdma_v5_0_reset_queue, > > + .reset =3D amdgpu_sdma_reset_queue_legacy, > >=20 > > }; > > =20 > > static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 5543e381dcca..e7f4b74f27= b4 > > 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > > @@ -1436,29 +1436,6 @@ static int sdma_v5_2_wait_for_idle(struct > > amdgpu_ip_block *ip_block)>=20 > > return -ETIMEDOUT; > > =20 > > } > >=20 > > -static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring, > > - unsigned int vmid, > > - struct amdgpu_fence=20 *timedout_fence) > > -{ > > - struct amdgpu_device *adev =3D ring->adev; > > - int r; > > - > > - if (ring->me >=3D adev->sdma.num_instances) { > > - dev_err(adev->dev, "sdma instance not found\n"); > > - return -EINVAL; > > - } > > - > > - amdgpu_ring_reset_helper_begin(ring, timedout_fence); > > - > > - amdgpu_amdkfd_suspend(adev, true); > > - r =3D amdgpu_sdma_reset_engine(adev, ring->me, true); > > - amdgpu_amdkfd_resume(adev, true); > > - if (r) > > - return r; > > - > > - return amdgpu_ring_reset_helper_end(ring, timedout_fence); > > -} > > - > >=20 > > static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring) > > { > > =20 > > u32 f32_cntl, freeze, cntl, stat1_reg; > >=20 > > @@ -1951,7 +1928,7 @@ static const struct amdgpu_ring_funcs > > sdma_v5_2_ring_funcs =3D {>=20 > > .emit_reg_write_reg_wait =3D=20 sdma_v5_2_ring_emit_reg_write_reg_wait, > > .init_cond_exec =3D sdma_v5_2_ring_init_cond_exec, > > .preempt_ib =3D sdma_v5_2_ring_preempt_ib, > >=20 > > - .reset =3D sdma_v5_2_reset_queue, > > + .reset =3D amdgpu_sdma_reset_queue_legacy, > >=20 > > }; > > =20 > > static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)