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[94.27.150.12]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24d6f203acsm279822566b.24.2026.08.24.08.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Aug 2026 08:07:42 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Petr Belyaev Cc: alexander.deucher@amd.com, Petr Belyaev Subject: Re: [PATCH] drm/amd/pm/smu7: Don't send VddC_Request on CI Date: Mon, 24 Aug 2026 17:07:41 +0200 Message-ID: In-Reply-To: <20260824144714.182835-1-upcfrost@gmail.com> References: <20260824144714.182835-1-upcfrost@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Monday, August 24, 2026 4:47:14=E2=80=AFPM Central European Summer Time = Petr=20 Belyaev wrote: > smu7_upload_dpm_level_enable_mask() calls > smu7_apply_minimum_dce_voltage_request() unconditionally, which sends > PPSMC_MSG_VddC_Request to the SMC. CI SMC firmware does not implement > that message: it is only defined in smu7_ppsmc.h, tonga_ppsmc.h and > fiji_ppsmc.h, and there is no CI equivalent. The SMC therefore never > writes SMC_RESP, PHM_WAIT_FIELD_UNEQUAL() spins until it gives up, and > every call burns the full ~1.9s response timeout. Hi, I'm sorry but this is wrong. I added the VDDC request specifically to solve an issue with a Bonaire GPU. That system will boot into a black screen without requesting a high enough= =20 voltage for the display engine. This patch would regress that. >=20 > Nothing downstream notices, because ci_send_msg_to_smc() returns 0 > regardless of the outcome. The only effects are the delay and >=20 > amdgpu: failed to send message 15f ret is 0 >=20 > in dmesg. On a Radeon R7 260X (BONAIRE, 1002:6658) this is 40 messages > per boot: 32 during the boot-time modeset, which becomes ~59s of blank > screen, and 8 more on every DPMS wake, adding ~15s before the display > comes back. How do you reproduce this issue, and on which kernel version? I've tested this patch on two different Bonaire chips and a Hawaii chip, an= d=20 haven't seen this error message. In fact I am running an R9 390X right now = and=20 I don't see this error message in my logs. >=20 > Commit 0138610c1413 ("drm/amd/pm/smu7: Fix SMU7 voltage dependency on > display clock") extended this feature to CI, which the previous > implementation had deliberately excluded -- the old call site was > guarded by pp_table_version =3D=3D PP_TABLE_V1 with an adjacent comment > reading "TO DO for v0 iceland and Ci". That commit was verified on a > Radeon R9 M380, which is VI, so the CI path went untested. The CI path definitely did not go untested. R9 M380 is Bonaire (it's in an old iMac). You can see all the details here: https://gitlab.freedesktop.org/drm/amd/-/work_items/3425#note_3338643 Best regards, Timur