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[94.27.154.94]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b5e8a0d143sm455024e87.63.2026.08.28.08.36.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 08:36:53 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Alexander.Deucher@amd.com, Christian =?UTF-8?B?S8O2bmln?= , Natalie Vock , Marek =?UTF-8?B?T2zFocOhaw==?= , Mario Limonciello , Tvrtko Ursulin , Felix Kuehling , "Lazar, Lijo" Subject: Re: [PATCH 4/5] drm/amdgpu/sdma: Use common SDMA legacy queue reset on SDMA v4.4.2 Date: Fri, 28 Aug 2026 17:36:52 +0200 Message-ID: In-Reply-To: <5158d162-f60c-4ef2-b2a2-cc544e1915f5@amd.com> References: <20260828120729.25908-1-timur.kristof@gmail.com> <20260828120729.25908-5-timur.kristof@gmail.com> <5158d162-f60c-4ef2-b2a2-cc544e1915f5@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Friday, August 28, 2026 4:16:15=E2=80=AFPM Central European Summer Time = Lazar, Lijo=20 wrote: > On 28-Aug-26 5:37 PM, Timur Krist=C3=B3f wrote: > > Besides sharing code, this additionally adds support for > > restoring queue contents after the reset. > >=20 > > Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 18 ++---------------- > > 1 file changed, 2 insertions(+), 16 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c > > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index > > 72ea9db939b4..023821848531 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c > > @@ -1655,20 +1655,6 @@ static bool sdma_v4_4_2_is_queue_selected(struct > > amdgpu_device *adev, uint32_t i>=20 > > return (context_status & SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK)=20 !=3D 0; > > =20 > > } > >=20 > > -static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, > > - unsigned int vmid, > > - struct amdgpu_fence=20 *timedout_fence) > > -{ > > - struct amdgpu_device *adev =3D ring->adev; > > - u32 id =3D ring->me; > > - int r; > > - > > - amdgpu_amdkfd_suspend(adev, true); > > - r =3D amdgpu_sdma_reset_engine(adev, id, false); >=20 > The common one passes true, so this doesn't look right. > amdgpu_sdma_reset_engine(adev, ring->me, true); >=20 >=20 > Thanks, > Lijo Can you please elaborate more on what you are suggesting here? The caller of the queue reset is amdgpu_job_timedout() and that function=20 already handles kernel queues. >=20 > > - amdgpu_amdkfd_resume(adev, true); > > - return r; > > -} > > - > >=20 > > static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring) > > { > > =20 > > struct amdgpu_device *adev =3D ring->adev; > >=20 > > @@ -2133,7 +2119,7 @@ static const struct amdgpu_ring_funcs > > sdma_v4_4_2_ring_funcs =3D {>=20 > > .emit_wreg =3D sdma_v4_4_2_ring_emit_wreg, > > .emit_reg_wait =3D sdma_v4_4_2_ring_emit_reg_wait, > > .emit_reg_write_reg_wait =3D=20 amdgpu_ring_emit_reg_write_reg_wait_helper, > >=20 > > - .reset =3D sdma_v4_4_2_reset_queue, > > + .reset =3D amdgpu_sdma_reset_queue_legacy, > >=20 > > }; > > =20 > > static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs =3D= { > >=20 > > @@ -2165,7 +2151,7 @@ static const struct amdgpu_ring_funcs > > sdma_v4_4_2_page_ring_funcs =3D {>=20 > > .emit_wreg =3D sdma_v4_4_2_ring_emit_wreg, > > .emit_reg_wait =3D sdma_v4_4_2_ring_emit_reg_wait, > > .emit_reg_write_reg_wait =3D=20 amdgpu_ring_emit_reg_write_reg_wait_helper, > >=20 > > - .reset =3D sdma_v4_4_2_reset_queue, > > + .reset =3D amdgpu_sdma_reset_queue_legacy, > >=20 > > }; > > =20 > > static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)