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[94.27.197.105]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f464c1f84sm9330314f8f.29.2026.07.14.08.39.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 08:39:43 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: Alex Deucher , Tvrtko Ursulin Cc: amd-gfx@lists.freedesktop.org, Alex Deucher , christian.koenig@amd.com, pierre-eric.pelloux-prayer@amd.com, Natalie Vock Subject: Re: [PATCH 1/9] drm/amdgpu/gfx7: Make amdgpu_gfx_mqd_sw_init() usable on GFX7 Date: Tue, 14 Jul 2026 17:39:41 +0200 Message-ID: In-Reply-To: <061761c8-cdd1-47d2-abcb-718711c49cef@ursulin.net> References: <20260713125838.30607-1-timur.kristof@gmail.com> <061761c8-cdd1-47d2-abcb-718711c49cef@ursulin.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Tuesday, July 14, 2026 5:19:57=E2=80=AFPM Central European Summer Time T= vrtko=20 Ursulin wrote: > On 14/07/2026 16:05, Alex Deucher wrote: > > On Tue, Jul 14, 2026 at 10:59=E2=80=AFAM Tvrtko Ursulin =20 wrote: > >> On 13/07/2026 13:58, Timur Krist=C3=B3f wrote: > >>> We don't use KIQ on GFX7 but otherwise MQD works the > >>> same way as GFX8 and newer. > >>>=20 > >>> Signed-off-by: Timur Krist=C3=B3f > >>> --- > >>>=20 > >>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +- > >>> 1 file changed, 1 insertion(+), 1 deletion(-) > >>>=20 > >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c > >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index > >>> 96c9d4f00b27..0f142c156afa 100644 > >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c > >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c > >>> @@ -420,7 +420,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device > >>> *adev, > >>>=20 > >>> #endif > >>> =20 > >>> /* create MQD for KIQ */ > >>>=20 > >>> - if (!adev->enable_mes_kiq && !ring->mqd_obj) { > >>> + if (adev->asic_type >=3D CHIP_TOPAZ && !adev->enable_mes_kiq && > >>> !ring->mqd_obj) {>>=20 > >> CHIP_TOPAZ is gfx7? Hm if it is then the branch would already run ther= e. > >> So the change is limiting the branch to a subset of platforms, while t= he > >> patch title made me think it is enabling something on gfx7. Perhaps > >> somehow indirectly or what am I not understanding? > >=20 > > TOPAZ is gfx8. We currently don't use KIQ on GFX7 so the patch changes the code to allocat= e=20 the BO only on GFX8 and newer. Topaz is the first GFX8 chip in the enum, so= =20 that's why the code checks >=3D TOPAZ here. > Ah now I get it, thank you! Could maybe adev->gfx[0].kiq.something or be > used to make it a bit self-documenting? Technically, GFX7 supports the KIQ, amdgpu just doesn't use it. So, I fear= =20 that adding a field would mislead the reader into thinking that the HW supp= ort=20 is missing when it really is just the kernel doesn't use it. How would you feel about just updating the comment above the changed line? Maybe like this? /* create MQD for KIQ - only on GFX8+ GPUs where we use the KIQ */ I think that would make it self-explanatory. >=20 > >>> /* originaly the KIQ MQD is put in GTT domain, but for > >>> SRIOV VRAM domain is a must>>> =20 > >>> * otherwise hypervisor trigger SAVE_VF fail after dri= ver > >>> unloaded which mean MQD * deallocated and gart_unbind, > >>> to strict diverage we decide to use VRAM domain for