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[84.1.217.106]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2a3523809fsm290712166b.5.2026.09.21.04.37.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 04:37:51 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: Christian =?UTF-8?B?S8O2bmln?= , Huang Yu Cc: Yu Huang , Honglei Huang , Ray Huang , Shen Junhua , Lingshan Zhu , Natalie Vock , AMD-GFX Subject: Re: [PATCH 03/13] drm/amdgpu: allocate and fill dummy PDs/PTs Date: Mon, 21 Sep 2026 13:37:50 +0200 Message-ID: In-Reply-To: <20260917110158.296198-4-yhuang13@amd.com> References: <20260917110158.296198-1-yhuang13@amd.com> <20260917110158.296198-4-yhuang13@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Thursday, September 17, 2026 1:01:48=E2=80=AFPM Central European Summer = Time Huang=20 Yu wrote: > From: Christian K=C3=B6nig >=20 > Allocate some PDs/PTs which just point to the dummy page. >=20 > Those can be used in page faults to redirect recoverable page faults > to the dummy page. >=20 > Signed-off-by: Christian K=C3=B6nig Makes good sense. Reviewed-by: Timur Krist=C3=B3f > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 +++- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 +- > .../gpu/drm/amd/amdgpu/amdgpu_vm_internal.h | 2 + > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 57 +++++++++++++++++++ > 4 files changed, 73 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 517490946a9c..5675925ca656 > 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > @@ -2843,8 +2843,10 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, > struct amdgpu_vm *vm) * > * Initialize the VM manager structures > */ > -void amdgpu_vm_manager_init(struct amdgpu_device *adev) > +int amdgpu_vm_manager_init(struct amdgpu_device *adev) > { > + int r; > + > /* Concurrent flushes are only possible starting with Vega10 and > * are broken on Navi10 and Navi14. > */ > @@ -2856,6 +2858,10 @@ void amdgpu_vm_manager_init(struct amdgpu_device > *adev) spin_lock_init(&adev->vm_manager.prt_lock); > atomic_set(&adev->vm_manager.num_prt_users, 0); >=20 > + r =3D amdgpu_vm_pt_alloc_dummies(adev); > + if (r) > + return r; > + > /* If not overridden by the user, by default, only in large BAR=20 systems > * Compute VM tables will be updated by CPU > */ > @@ -2875,6 +2881,8 @@ void amdgpu_vm_manager_init(struct amdgpu_device > *adev) #else > adev->vm_manager.vm_update_mode =3D 0; > #endif > + > + return 0; > } >=20 > /** > @@ -2886,6 +2894,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device > *adev) */ > void amdgpu_vm_manager_fini(struct amdgpu_device *adev) > { > + amdgpu_vm_pt_free_dummies(adev); > amdgpu_vmid_mgr_fini(adev); > amdgpu_pasid_mgr_cleanup(); > } > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index ac3b8e8525c1..826406522b24 > 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > @@ -409,6 +409,9 @@ struct amdgpu_vm_manager { >=20 > /* Global registration of recent page fault information */ > struct amdgpu_vm_fault_info fault_info; > + > + struct amdgpu_bo *dummy_pd[AMDGPU_VM_PTB + 1]; > + uint64_t dummy_dst[AMDGPU_VM_PTB + 1]; > }; >=20 > struct amdgpu_bo_va_mapping; > @@ -420,7 +423,7 @@ struct amdgpu_bo_va_mapping; > extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; > extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; >=20 > -void amdgpu_vm_manager_init(struct amdgpu_device *adev); > +int amdgpu_vm_manager_init(struct amdgpu_device *adev); > void amdgpu_vm_manager_fini(struct amdgpu_device *adev); >=20 > long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_internal.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_internal.h index > 447195cc4593..16cc0d5f5894 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_internal.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_internal.h > @@ -125,6 +125,8 @@ void amdgpu_vm_pt_free_work(struct work_struct *work); > void amdgpu_vm_pt_free_list(struct amdgpu_device *adev, > struct amdgpu_vm_update_params *params); > int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm > *vm); +int amdgpu_vm_pt_alloc_dummies(struct amdgpu_device *adev); > +void amdgpu_vm_pt_free_dummies(struct amdgpu_device *adev); >=20 > /* > * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-= =46S > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index > b85b70a1a428..3a6449d60988 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c > @@ -963,3 +963,60 @@ int amdgpu_vm_pt_map_tables(struct amdgpu_device *ad= ev, > struct amdgpu_vm *vm) >=20 > return 0; > } > + > +/* amdgpu_vm_pt_alloc_dummies - allocate dummy PDs/PTs > + * > + * @adev: the amdgpu device pointer > + * > + * Allocate some dummy PDs/PTs which can be used to redirect page faults= to > the + * dummy page. > + */ > +int amdgpu_vm_pt_alloc_dummies(struct amdgpu_device *adev) > +{ > + struct amdgpu_vm_manager *vm_mgr =3D &adev->vm_manager; > + int r; > + > + for (int level =3D AMDGPU_VM_PTB; level !=3D vm_mgr->root_level;=20 level--) { > + size_t size =3D amdgpu_vm_pt_size(adev, level); > + uint64_t addr, flags; > + void *ptr; > + > + r =3D amdgpu_bo_create_kernel(adev, size, 0, > + =20 AMDGPU_GEM_DOMAIN_VRAM, > + &vm_mgr- >dummy_pd[level], > + &vm_mgr- >dummy_dst[level], > + &ptr); > + if (r) > + return r; > + > + if (level =3D=3D AMDGPU_VM_PTB) { > + addr =3D adev->dummy_page_addr; > + /* > + * TODO: We want to have separate dummies for=20 reads and > + * writes. > + */ > + flags =3D AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED=20 | > + AMDGPU_PTE_SYSTEM |=20 AMDGPU_PTE_EXECUTABLE | > + AMDGPU_PTE_READABLE |=20 AMDGPU_PTE_WRITEABLE; > + } else { > + amdgpu_gmc_get_pde_for_bo(vm_mgr- >dummy_pd[level + 1], > + level,=20 &addr, &flags); > + } > + > + for (int i =3D 0; i < amdgpu_vm_pt_num_entries(adev,=20 level); i++) > + amdgpu_gmc_set_pte_pde(adev, ptr, i, addr,=20 flags); > + } > + > + return 0; > +} > + > +void amdgpu_vm_pt_free_dummies(struct amdgpu_device *adev) > +{ > + struct amdgpu_vm_manager *vm_mgr =3D &adev->vm_manager; > + void *ptr; > + > + for (int level =3D AMDGPU_VM_PTB; level !=3D vm_mgr->root_level;=20 level--) > + amdgpu_bo_free_kernel(&vm_mgr->dummy_pd[level], > + &vm_mgr->dummy_dst[level], > + &ptr); > +}