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[194.118.146.41]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd9c001dsm134822975e9.12.2026.10.16.03.07.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 03:07:54 -0700 (PDT) From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, Navid Ghahremani , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arnd@arndb.de, linux@armlinux.org.uk, robh@kernel.org, krzk@kernel.org Subject: Re: [PATCH 09/24] gpio: Add ZTE ZX279128S GPIO driver Date: Fri, 16 Oct 2026 12:07:45 +0200 Message-ID: In-Reply-To: References: <20261010130024.177503-1-ghahramani.navid@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPartW3qWXJSyTHGnhsggtEkzAg"; micalg="pgp-sha256"; protocol="application/pgp-signature" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261016_030758_606193_486991C4 X-CRM114-Status: GOOD ( 26.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --nextPartW3qWXJSyTHGnhsggtEkzAg Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: Linus Walleij Subject: Re: [PATCH 09/24] gpio: Add ZTE ZX279128S GPIO driver Date: Fri, 16 Oct 2026 12:07:45 +0200 Message-ID: In-Reply-To: MIME-Version: 1.0 Hi Linus, Am Freitag, 16. Oktober 2026, 11:07:48 Mitteleurop=C3=A4ische Sommerzeit sc= hrieb=20 Linus Walleij: > I don't believe that the hardware block inside the SoC actually > has a single inverted direction bit. Prove it =F0=9F=98=80 >=20 > This sounds much more like someone using open drain to drive > the line high when setting it to input mode and has hacked > their way around that behaviour instead of just asking the > GPIOlib core to do the right thing: >=20 > gpios =3D <&gpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; I read up a bit on open drain configurations and I can't rule out your theo= ry,=20 but I think it is unlikely. The following is from memory of my testing two= =20 months ago or so: On all GPIOs of my zx29 board except GPIO 24, direction=3D1 means output,=20 direction=3D0 means input. =46or GPIO 24, if I set direction=3D1 and use the pull-up or pull-down, I c= an read=20 back the bias state via the GPIO input register. The GPIO output register i= s=20 ignored. So it is behaving very input-y. Bias on this gpio defaults to no=20 bias. Both pull-down (reads 0) and pull-up (reads 1) work that way. With direction=3D0, the gpio output gets read back on the gpio input regard= less=20 of bias. I.e. the GPIO overpowers the bias as it should for output. The GPIO in question is used to keep the device enabled when running on=20 battery. ZTE's code calls it "PSHOLD". My best guess is that they wired it = up=20 in that way so that the default hardware state, direction=3D0, value=3D0, d= rives=20 it low and shuts off the device unless the software takes action to keep th= e=20 device powered. The practical outcome is that the user has to hold the powe= r=20 button for ~1 second until ZTE's U-Boot sets direction=3D0, value=3D1 to ke= ep the=20 device running. Do you have any other ideas I could try? I do need GPIO 27 or so for the SPI display D/C pin, which sits in the same= =20 byte, so I can't just declare GPIO 24 with a "dirin" reg. > It does sounds a bit like churn if we remove a driver from the kernel > and then add it back after some years... >=20 > However if this is using GENERIC_GPIO (regmap is something else) > this is a better base. >=20 > I think it's easy for an LLM to port over the IRQ support from the > old driver to this new one, given the code is already there and > this way keep the best of both worlds? You probably mean GPIO_GENERIC, which afaiu is implemented in gpio-mmio.c.= =20 That's what I am actually using (I guess I confused this with gpio-regmap i= n=20 my previous email). But my hardware (unlike Navid's) has no GPIO IRQs. (The SoC kinda has GPIO IRQs, but those are handled via pinmux. A few lines= =20 can be connected to the GIC, bypassing GPIO entirely) --nextPartW3qWXJSyTHGnhsggtEkzAg Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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