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[94.27.154.94]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255f1b1fdasm456873266b.37.2026.08.31.06.35.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 06:35:11 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: christian.koenig@amd.com, amd-gfx@lists.freedesktop.org, Arunpravin Paneer Selvam Cc: alexander.deucher@amd.com, Arunpravin Paneer Selvam , stable@vger.kernel.org Subject: Re: [PATCH v2] drm/amdgpu: skip the VMID 0 flush for VRAM clear-on-release Date: Mon, 31 Aug 2026 15:35:11 +0200 Message-ID: In-Reply-To: <20260831122841.42160-1-Arunpravin.PaneerSelvam@amd.com> References: <20260831122841.42160-1-Arunpravin.PaneerSelvam@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Monday, August 31, 2026 2:28:41=E2=80=AFPM Central European Summer Time = Arunpravin=20 Paneer Selvam wrote: > Clear-on-release only runs on VRAM, which amdgpu_ttm_map_buffer() reaches > via its direct MC address without programming a GART window, yet the wipe > still forces a VMID 0 flush. On GFX11 (e.g. Navi33) that spurious SDMA > flush can wedge the engine; only flush when a GART window is actually use= d. >=20 > v2: Let amdgpu_ttm_map_buffer() return whether the VMID 0 flush is needed, > and drive the clear and copy paths from that. (Christian) >=20 > Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality") > Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5413 > Cc: stable@vger.kernel.org > Cc: Christian K=C3=B6nig > Signed-off-by: Arunpravin Paneer Selvam Looks good, thank you! Reviewed-by: Timur Krist=C3=B3f > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 22 ++++++++++++++++------ > 1 file changed, 16 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index > 6c07cee8e8777..e0bdd95c64de8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > @@ -190,6 +190,8 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, str= uct > amdgpu_ttm_buffer_entit * @tmz: if we should setup a TMZ enabled mapping > * @size: in number of bytes to map, out number of bytes mapped > * @addr: resulting address inside the MC address space > + * @vm_needs_flush: out, set true if a GART window was programmed (VMID 0 > flush + * needed) or false for a direct address; may be NULL > * > * Setup one of the GART windows to access a specific piece of memory or > return * the physical address for local memory. > @@ -199,7 +201,8 @@ static int amdgpu_ttm_map_buffer(struct > amdgpu_ttm_buffer_entity *entity, struct ttm_resource *mem, > struct amdgpu_res_cursor=20 *mm_cur, > unsigned int window, > - bool tmz, uint64_t *size,=20 uint64_t *addr) > + bool tmz, uint64_t *size,=20 uint64_t *addr, > + bool *vm_needs_flush) > { > struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->bdev); > unsigned int offset, num_pages, num_dw, num_bytes; > @@ -220,9 +223,14 @@ static int amdgpu_ttm_map_buffer(struct > amdgpu_ttm_buffer_entity *entity, if (!tmz && mem->start !=3D > AMDGPU_BO_INVALID_OFFSET) { > *addr =3D amdgpu_ttm_domain_start(adev, mem->mem_type) + > mm_cur->start; > + if (vm_needs_flush) > + *vm_needs_flush =3D false; > return 0; > } >=20 > + /* A GART window is programmed below, so its VMID 0 TLB needs a=20 flush */ > + if (vm_needs_flush) > + *vm_needs_flush =3D true; >=20 > /* > * If start begins at an offset inside the page, then adjust the=20 size > @@ -322,6 +330,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct > amdgpu_device *adev, while (src_mm.remaining) { > uint64_t from, to, cur_size, tiling_flags; > uint32_t num_type, data_format, max_com,=20 write_compress_disable; > + bool src_vm_flush, dst_vm_flush; > struct dma_fence *next; >=20 > /* Never copy more than 256MiB at once to avoid a=20 timeout */ > @@ -329,12 +338,12 @@ static int amdgpu_ttm_copy_mem_to_mem(struct > amdgpu_device *adev, >=20 > /* Map src to window 0 and dst to window 1. */ > r =3D amdgpu_ttm_map_buffer(entity, src->bo, src->mem,=20 &src_mm, > - 0, tmz, &cur_size,=20 &from); > + 0, tmz, &cur_size,=20 &from, &src_vm_flush); > if (r) > goto error; >=20 > r =3D amdgpu_ttm_map_buffer(entity, dst->bo, dst->mem,=20 &dst_mm, > - 1, tmz, &cur_size,=20 &to); > + 1, tmz, &cur_size,=20 &to, &dst_vm_flush); > if (r) > goto error; >=20 > @@ -362,7 +371,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct > amdgpu_device *adev, } >=20 > r =3D amdgpu_copy_buffer(adev, entity, from, to, cur_size,=20 resv, > - &next, true, copy_flags); > + &next, src_vm_flush ||=20 dst_vm_flush, copy_flags); > if (r) > goto error; >=20 > @@ -2578,6 +2587,7 @@ int amdgpu_ttm_clear_buffer(struct > amdgpu_ttm_buffer_entity *entity, struct amdgpu_device *adev =3D > amdgpu_ttm_adev(bo->tbo.bdev); > struct dma_fence *fence =3D NULL; > struct amdgpu_res_cursor dst; > + bool vm_needs_flush =3D false; > int r; >=20 > if (!entity) > @@ -2599,13 +2609,13 @@ int amdgpu_ttm_clear_buffer(struct > amdgpu_ttm_buffer_entity *entity, cur_size =3D min(dst.size, 256ULL << 20= ); >=20 > r =3D amdgpu_ttm_map_buffer(entity, &bo->tbo, bo- >tbo.resource, &dst, > - 0, false, &cur_size,=20 &to); > + 0, false, &cur_size,=20 &to, &vm_needs_flush); > if (r) > goto error; >=20 > r =3D amdgpu_ttm_fill_mem(adev, entity, > 0, to, cur_size, resv, > - &next, true,=20 k_job_id); > + &next, vm_needs_flush,=20 k_job_id); > if (r) > goto error;