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Wed, 23 Dec 2020 00:21:05 -0800 (PST) Date: Wed, 23 Dec 2020 17:20:58 +0900 From: Tomasz Figa To: Yong Wu Subject: Re: [PATCH v5 09/27] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Message-ID: References: <20201209080102.26626-1-yong.wu@mediatek.com> <20201209080102.26626-10-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201209080102.26626-10-yong.wu@mediatek.com> Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, Tomasz Figa , Will Deacon , linux-kernel@vger.kernel.org, Evan Green , chao.hao@mediatek.com, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , Matthias Brugger , anan.sun@mediatek.com, Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, Dec 09, 2020 at 04:00:44PM +0800, Yong Wu wrote: > MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34. > > Signed-off-by: Yong Wu > Acked-by: Will Deacon > Reviewed-by: Robin Murphy > --- > drivers/iommu/io-pgtable-arm-v7s.c | 9 +++++++-- > drivers/iommu/mtk_iommu.c | 2 +- > include/linux/io-pgtable.h | 4 ++-- > 3 files changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c > index e880745ab1e8..4d0aa079470f 100644 > --- a/drivers/iommu/io-pgtable-arm-v7s.c > +++ b/drivers/iommu/io-pgtable-arm-v7s.c > @@ -112,9 +112,10 @@ > #define ARM_V7S_TEX_MASK 0x7 > #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) > > -/* MediaTek extend the two bits for PA 32bit/33bit */ > +/* MediaTek extend the bits below for PA 32bit/33bit/34bit */ > #define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9) > #define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4) > +#define ARM_V7S_ATTR_MTK_PA_BIT34 BIT(5) > > /* *well, except for TEX on level 2 large pages, of course :( */ > #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6 > @@ -194,6 +195,8 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, > pte |= ARM_V7S_ATTR_MTK_PA_BIT32; > if (paddr & BIT_ULL(33)) > pte |= ARM_V7S_ATTR_MTK_PA_BIT33; > + if (paddr & BIT_ULL(34)) > + pte |= ARM_V7S_ATTR_MTK_PA_BIT34; > return pte; > } > > @@ -218,6 +221,8 @@ static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, > paddr |= BIT_ULL(32); > if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) > paddr |= BIT_ULL(33); > + if (pte & ARM_V7S_ATTR_MTK_PA_BIT34) > + paddr |= BIT_ULL(34); > return paddr; > } > > @@ -754,7 +759,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > if (cfg->ias > ARM_V7S_ADDR_BITS) > return NULL; > > - if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) > + if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS)) > return NULL; > > if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 6451d83753e1..ec3c87d4b172 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -320,7 +320,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) > IO_PGTABLE_QUIRK_ARM_MTK_EXT, > .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, > .ias = 32, > - .oas = 34, > + .oas = 35, Shouldn't this be set according to the real hardware capabilities, instead of always setting it to 35? Best regards, Tomasz > .tlb = &mtk_iommu_flush_ops, > .iommu_dev = data->dev, > }; > diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h > index 4cde111e425b..1ae0757f4f94 100644 > --- a/include/linux/io-pgtable.h > +++ b/include/linux/io-pgtable.h > @@ -77,8 +77,8 @@ struct io_pgtable_cfg { > * TLB maintenance when mapping as well as when unmapping. > * > * IO_PGTABLE_QUIRK_ARM_MTK_EXT: (ARM v7s format) MediaTek IOMMUs extend > - * to support up to 34 bits PA where the bit32 and bit33 are > - * encoded in the bit9 and bit4 of the PTE respectively. > + * to support up to 35 bits PA where the bit32, bit33 and bit34 are > + * encoded in the bit9, bit4 and bit5 of the PTE respectively. > * > * IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs > * on unmap, for DMA domains using the flush queue mechanism for > -- > 2.18.0 > > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78547C433DB for ; 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Wed, 23 Dec 2020 00:21:05 -0800 (PST) Received: from chromium.org ([2401:fa00:8f:2:a28c:fdff:fef0:43bf]) by smtp.gmail.com with ESMTPSA id gb9sm7480288pjb.40.2020.12.23.00.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Dec 2020 00:21:05 -0800 (PST) Date: Wed, 23 Dec 2020 17:20:58 +0900 From: Tomasz Figa To: Yong Wu Subject: Re: [PATCH v5 09/27] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Message-ID: References: <20201209080102.26626-1-yong.wu@mediatek.com> <20201209080102.26626-10-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201209080102.26626-10-yong.wu@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201223_032108_203412_A1CA26A1 X-CRM114-Status: GOOD ( 25.10 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, Tomasz Figa , Will Deacon , Joerg Roedel , linux-kernel@vger.kernel.org, Evan Green , chao.hao@mediatek.com, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , Matthias Brugger , anan.sun@mediatek.com, Robin Murphy , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Wed, Dec 09, 2020 at 04:00:44PM +0800, Yong Wu wrote: > MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34. > > Signed-off-by: Yong Wu > Acked-by: Will Deacon > Reviewed-by: Robin Murphy > --- > drivers/iommu/io-pgtable-arm-v7s.c | 9 +++++++-- > drivers/iommu/mtk_iommu.c | 2 +- > include/linux/io-pgtable.h | 4 ++-- > 3 files changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c > index e880745ab1e8..4d0aa079470f 100644 > --- a/drivers/iommu/io-pgtable-arm-v7s.c > +++ b/drivers/iommu/io-pgtable-arm-v7s.c > @@ -112,9 +112,10 @@ > #define ARM_V7S_TEX_MASK 0x7 > #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) > > -/* MediaTek extend the two bits for PA 32bit/33bit */ > +/* MediaTek extend the bits below for PA 32bit/33bit/34bit */ > #define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9) > #define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4) > +#define ARM_V7S_ATTR_MTK_PA_BIT34 BIT(5) > > /* *well, except for TEX on level 2 large pages, of course :( */ > #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6 > @@ -194,6 +195,8 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, > pte |= ARM_V7S_ATTR_MTK_PA_BIT32; > if (paddr & BIT_ULL(33)) > pte |= ARM_V7S_ATTR_MTK_PA_BIT33; > + if (paddr & BIT_ULL(34)) > + pte |= ARM_V7S_ATTR_MTK_PA_BIT34; > return pte; > } > > @@ -218,6 +221,8 @@ static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, > paddr |= BIT_ULL(32); > if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) > paddr |= BIT_ULL(33); > + if (pte & ARM_V7S_ATTR_MTK_PA_BIT34) > + paddr |= BIT_ULL(34); > return paddr; > } > > @@ -754,7 +759,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > if (cfg->ias > ARM_V7S_ADDR_BITS) > return NULL; > > - if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) > + if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS)) > return NULL; > > if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 6451d83753e1..ec3c87d4b172 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -320,7 +320,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) > IO_PGTABLE_QUIRK_ARM_MTK_EXT, > .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, > .ias = 32, > - .oas = 34, > + .oas = 35, Shouldn't this be set according to the real hardware capabilities, instead of always setting it to 35? Best regards, Tomasz > .tlb = &mtk_iommu_flush_ops, > .iommu_dev = data->dev, > }; > diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h > index 4cde111e425b..1ae0757f4f94 100644 > --- a/include/linux/io-pgtable.h > +++ b/include/linux/io-pgtable.h > @@ -77,8 +77,8 @@ struct io_pgtable_cfg { > * TLB maintenance when mapping as well as when unmapping. > * > * IO_PGTABLE_QUIRK_ARM_MTK_EXT: (ARM v7s format) MediaTek IOMMUs extend > - * to support up to 34 bits PA where the bit32 and bit33 are > - * encoded in the bit9 and bit4 of the PTE respectively. > + * to support up to 35 bits PA where the bit32, bit33 and bit34 are > + * encoded in the bit9, bit4 and bit5 of the PTE respectively. > * > * IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs > * on unmap, for DMA domains using the flush queue mechanism for > -- > 2.18.0 > > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AC4AC433E0 for ; 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Wed, 23 Dec 2020 00:21:05 -0800 (PST) Received: from chromium.org ([2401:fa00:8f:2:a28c:fdff:fef0:43bf]) by smtp.gmail.com with ESMTPSA id gb9sm7480288pjb.40.2020.12.23.00.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Dec 2020 00:21:05 -0800 (PST) Date: Wed, 23 Dec 2020 17:20:58 +0900 From: Tomasz Figa To: Yong Wu Subject: Re: [PATCH v5 09/27] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Message-ID: References: <20201209080102.26626-1-yong.wu@mediatek.com> <20201209080102.26626-10-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201209080102.26626-10-yong.wu@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201223_032107_900990_90B78288 X-CRM114-Status: GOOD ( 26.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, Tomasz Figa , Will Deacon , Joerg Roedel , linux-kernel@vger.kernel.org, Evan Green , chao.hao@mediatek.com, iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , Matthias Brugger , anan.sun@mediatek.com, Robin Murphy , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Dec 09, 2020 at 04:00:44PM +0800, Yong Wu wrote: > MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34. > > Signed-off-by: Yong Wu > Acked-by: Will Deacon > Reviewed-by: Robin Murphy > --- > drivers/iommu/io-pgtable-arm-v7s.c | 9 +++++++-- > drivers/iommu/mtk_iommu.c | 2 +- > include/linux/io-pgtable.h | 4 ++-- > 3 files changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c > index e880745ab1e8..4d0aa079470f 100644 > --- a/drivers/iommu/io-pgtable-arm-v7s.c > +++ b/drivers/iommu/io-pgtable-arm-v7s.c > @@ -112,9 +112,10 @@ > #define ARM_V7S_TEX_MASK 0x7 > #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) > > -/* MediaTek extend the two bits for PA 32bit/33bit */ > +/* MediaTek extend the bits below for PA 32bit/33bit/34bit */ > #define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9) > #define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4) > +#define ARM_V7S_ATTR_MTK_PA_BIT34 BIT(5) > > /* *well, except for TEX on level 2 large pages, of course :( */ > #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6 > @@ -194,6 +195,8 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, > pte |= ARM_V7S_ATTR_MTK_PA_BIT32; > if (paddr & BIT_ULL(33)) > pte |= ARM_V7S_ATTR_MTK_PA_BIT33; > + if (paddr & BIT_ULL(34)) > + pte |= ARM_V7S_ATTR_MTK_PA_BIT34; > return pte; > } > > @@ -218,6 +221,8 @@ static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, > paddr |= BIT_ULL(32); > if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) > paddr |= BIT_ULL(33); > + if (pte & ARM_V7S_ATTR_MTK_PA_BIT34) > + paddr |= BIT_ULL(34); > return paddr; > } > > @@ -754,7 +759,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > if (cfg->ias > ARM_V7S_ADDR_BITS) > return NULL; > > - if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) > + if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS)) > return NULL; > > if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 6451d83753e1..ec3c87d4b172 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -320,7 +320,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) > IO_PGTABLE_QUIRK_ARM_MTK_EXT, > .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, > .ias = 32, > - .oas = 34, > + .oas = 35, Shouldn't this be set according to the real hardware capabilities, instead of always setting it to 35? Best regards, Tomasz > .tlb = &mtk_iommu_flush_ops, > .iommu_dev = data->dev, > }; > diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h > index 4cde111e425b..1ae0757f4f94 100644 > --- a/include/linux/io-pgtable.h > +++ b/include/linux/io-pgtable.h > @@ -77,8 +77,8 @@ struct io_pgtable_cfg { > * TLB maintenance when mapping as well as when unmapping. > * > * IO_PGTABLE_QUIRK_ARM_MTK_EXT: (ARM v7s format) MediaTek IOMMUs extend > - * to support up to 34 bits PA where the bit32 and bit33 are > - * encoded in the bit9 and bit4 of the PTE respectively. > + * to support up to 35 bits PA where the bit32, bit33 and bit34 are > + * encoded in the bit9, bit4 and bit5 of the PTE respectively. > * > * IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs > * on unmap, for DMA domains using the flush queue mechanism for > -- > 2.18.0 > > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6744C433DB for ; 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Wed, 23 Dec 2020 00:21:05 -0800 (PST) Received: from chromium.org ([2401:fa00:8f:2:a28c:fdff:fef0:43bf]) by smtp.gmail.com with ESMTPSA id gb9sm7480288pjb.40.2020.12.23.00.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Dec 2020 00:21:05 -0800 (PST) Date: Wed, 23 Dec 2020 17:20:58 +0900 From: Tomasz Figa To: Yong Wu Cc: Joerg Roedel , Matthias Brugger , Rob Herring , Will Deacon , Robin Murphy , youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, Krzysztof Kozlowski , anan.sun@mediatek.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 09/27] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Message-ID: References: <20201209080102.26626-1-yong.wu@mediatek.com> <20201209080102.26626-10-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201209080102.26626-10-yong.wu@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Dec 09, 2020 at 04:00:44PM +0800, Yong Wu wrote: > MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34. > > Signed-off-by: Yong Wu > Acked-by: Will Deacon > Reviewed-by: Robin Murphy > --- > drivers/iommu/io-pgtable-arm-v7s.c | 9 +++++++-- > drivers/iommu/mtk_iommu.c | 2 +- > include/linux/io-pgtable.h | 4 ++-- > 3 files changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c > index e880745ab1e8..4d0aa079470f 100644 > --- a/drivers/iommu/io-pgtable-arm-v7s.c > +++ b/drivers/iommu/io-pgtable-arm-v7s.c > @@ -112,9 +112,10 @@ > #define ARM_V7S_TEX_MASK 0x7 > #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) > > -/* MediaTek extend the two bits for PA 32bit/33bit */ > +/* MediaTek extend the bits below for PA 32bit/33bit/34bit */ > #define ARM_V7S_ATTR_MTK_PA_BIT32 BIT(9) > #define ARM_V7S_ATTR_MTK_PA_BIT33 BIT(4) > +#define ARM_V7S_ATTR_MTK_PA_BIT34 BIT(5) > > /* *well, except for TEX on level 2 large pages, of course :( */ > #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6 > @@ -194,6 +195,8 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl, > pte |= ARM_V7S_ATTR_MTK_PA_BIT32; > if (paddr & BIT_ULL(33)) > pte |= ARM_V7S_ATTR_MTK_PA_BIT33; > + if (paddr & BIT_ULL(34)) > + pte |= ARM_V7S_ATTR_MTK_PA_BIT34; > return pte; > } > > @@ -218,6 +221,8 @@ static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl, > paddr |= BIT_ULL(32); > if (pte & ARM_V7S_ATTR_MTK_PA_BIT33) > paddr |= BIT_ULL(33); > + if (pte & ARM_V7S_ATTR_MTK_PA_BIT34) > + paddr |= BIT_ULL(34); > return paddr; > } > > @@ -754,7 +759,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > if (cfg->ias > ARM_V7S_ADDR_BITS) > return NULL; > > - if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) > + if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS)) > return NULL; > > if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 6451d83753e1..ec3c87d4b172 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -320,7 +320,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) > IO_PGTABLE_QUIRK_ARM_MTK_EXT, > .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, > .ias = 32, > - .oas = 34, > + .oas = 35, Shouldn't this be set according to the real hardware capabilities, instead of always setting it to 35? Best regards, Tomasz > .tlb = &mtk_iommu_flush_ops, > .iommu_dev = data->dev, > }; > diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h > index 4cde111e425b..1ae0757f4f94 100644 > --- a/include/linux/io-pgtable.h > +++ b/include/linux/io-pgtable.h > @@ -77,8 +77,8 @@ struct io_pgtable_cfg { > * TLB maintenance when mapping as well as when unmapping. > * > * IO_PGTABLE_QUIRK_ARM_MTK_EXT: (ARM v7s format) MediaTek IOMMUs extend > - * to support up to 34 bits PA where the bit32 and bit33 are > - * encoded in the bit9 and bit4 of the PTE respectively. > + * to support up to 35 bits PA where the bit32, bit33 and bit34 are > + * encoded in the bit9, bit4 and bit5 of the PTE respectively. > * > * IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs > * on unmap, for DMA domains using the flush queue mechanism for > -- > 2.18.0 > > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu