From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 071B2C433FE for ; Sun, 6 Dec 2020 20:17:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C64112310B for ; Sun, 6 Dec 2020 20:17:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727874AbgLFURg (ORCPT ); Sun, 6 Dec 2020 15:17:36 -0500 Received: from mail-pj1-f66.google.com ([209.85.216.66]:38866 "EHLO mail-pj1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726731AbgLFURf (ORCPT ); Sun, 6 Dec 2020 15:17:35 -0500 Received: by mail-pj1-f66.google.com with SMTP id j13so6234151pjz.3 for ; Sun, 06 Dec 2020 12:17:20 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=R+rjdl/kMmpfvATyyiBKTTDC7/ADOrYG2LQ26ycg4ts=; b=Fg5iNSadCdU0fE3KrYMtyWfsM7NrcfzglTVn0Nc8EsPkxuGpfn1nEXi2Jjvyat+dV9 6D8pEsfdgDt15WHyOrgl2yt6aCT3ie5cYQJZ5EJPJ7r29qs3gX0Sg96to4lTEWOkx4W5 ZQr28/EDjZ75bHaBkVaj38yuBzwuAfW/lrvG33K/csWEiPOfSjWlPXz7J+EU1FR/h/ax k/DyzvT0jKD0T8nOVaVjM01kwKfhH2nMZbfnv0JK0Rjp0TR3C5V/58MuOxUnB5NzJ6Hv KdWNkLlxNaib26Sc5l/byCeCJTLKHFeGkfix8znQaxoDH7aeJoFFbZbmVGC4DXOXQ1G6 Rjsg== X-Gm-Message-State: AOAM532OJbgoYlcm8+r5qmErUBHNnQIFdVW9ome2KKyvItbwL5h5+mYm zMI/2Fb9n2txIblIprf4sns= X-Google-Smtp-Source: ABdhPJxpA9QCLH2CckDZiO4WQ7tusbQz3TsQfr9LJIt6xF7N6IQbRIyD2evK2VHZgjLCDBw3mAerWw== X-Received: by 2002:a17:90a:990a:: with SMTP id b10mr2206383pjp.87.1607285815024; Sun, 06 Dec 2020 12:16:55 -0800 (PST) Received: from rocinante ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id w11sm12784288pfi.162.2020.12.06.12.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 12:16:54 -0800 (PST) Date: Sun, 6 Dec 2020 21:16:36 +0100 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Rob Herring , Jonathan Cameron , Jonathan Chocron , Shawn Lin , Heiko Stuebner , Zhou Wang , Lorenzo Pieralisi , Will Deacon , Robert Richter , Michal Simek , Toan Le , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Thomas Petazzoni , Nicolas Saenz Julienne , Florian Fainelli , Ray Jui , Scott Branden , Jonathan Derrick , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com Subject: Re: [PATCH v6 1/5] PCI: Unify ECAM constants in native PCI Express drivers Message-ID: References: <20201129230743.3006978-1-kw@linux.com> <20201129230743.3006978-2-kw@linux.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20201129230743.3006978-2-kw@linux.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hello Nicolas, Florian and Florian, [...] > -/* Configuration space read/write support */ > -static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) > -{ > - return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) > - | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) > - | (busnr << PCIE_EXT_BUSNUM_SHIFT) > - | (reg & ~3); > -} > - > static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, > int where) > { > @@ -716,7 +704,7 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, > return PCI_SLOT(devfn) ? NULL : base + where; > > /* For devices, write to the config space index register */ > - idx = brcm_pcie_cfg_index(bus->number, devfn, 0); > + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); > writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); > return base + PCIE_EXT_CFG_DATA + where; > } [...] Passing the hard-coded 0 as the "reg" argument here never actually did anything, thus the 32 bit alignment was never correctly enforced. My question would be: should this be 32 bit aligned? It seems like the intention was to perhaps make the alignment? I am sadly not intimately familiar with his hardware, so I am not sure if there is something to fix here or not. Also, I wonder whether it would be safe to pass the offset (the "where" variable) rather than hard-coded 0? Thank you for help in advance! Bjorn also asked the same question: https://lore.kernel.org/linux-pci/20201120203428.GA272511@bjorn-Precision-5520/ Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF55CC4361B for ; Sun, 6 Dec 2020 20:17:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 80AAB2310B for ; Sun, 6 Dec 2020 20:17:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 80AAB2310B Authentication-Results: mail.kernel.org; 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Sun, 06 Dec 2020 12:16:55 -0800 (PST) Received: from rocinante ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id w11sm12784288pfi.162.2020.12.06.12.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 12:16:54 -0800 (PST) Date: Sun, 6 Dec 2020 21:16:36 +0100 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Bjorn Helgaas Subject: Re: [PATCH v6 1/5] PCI: Unify ECAM constants in native PCI Express drivers Message-ID: References: <20201129230743.3006978-1-kw@linux.com> <20201129230743.3006978-2-kw@linux.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201129230743.3006978-2-kw@linux.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201206_151657_659236_EFB66798 X-CRM114-Status: GOOD ( 14.72 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heiko Stuebner , Benjamin Herrenschmidt , Shawn Lin , Paul Mackerras , Thomas Petazzoni , Jonathan Chocron , Toan Le , Will Deacon , Rob Herring , Lorenzo Pieralisi , Michael Ellerman , Michal Simek , linux-rockchip@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, Jonathan Derrick , linux-pci@vger.kernel.org, Ray Jui , Florian Fainelli , linux-rpi-kernel@lists.infradead.org, Jonathan Cameron , linux-arm-kernel@lists.infradead.org, Scott Branden , Zhou Wang , Robert Richter , linuxppc-dev@lists.ozlabs.org, Nicolas Saenz Julienne Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Hello Nicolas, Florian and Florian, [...] > -/* Configuration space read/write support */ > -static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) > -{ > - return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) > - | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) > - | (busnr << PCIE_EXT_BUSNUM_SHIFT) > - | (reg & ~3); > -} > - > static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, > int where) > { > @@ -716,7 +704,7 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, > return PCI_SLOT(devfn) ? NULL : base + where; > > /* For devices, write to the config space index register */ > - idx = brcm_pcie_cfg_index(bus->number, devfn, 0); > + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); > writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); > return base + PCIE_EXT_CFG_DATA + where; > } [...] Passing the hard-coded 0 as the "reg" argument here never actually did anything, thus the 32 bit alignment was never correctly enforced. My question would be: should this be 32 bit aligned? It seems like the intention was to perhaps make the alignment? I am sadly not intimately familiar with his hardware, so I am not sure if there is something to fix here or not. Also, I wonder whether it would be safe to pass the offset (the "where" variable) rather than hard-coded 0? Thank you for help in advance! Bjorn also asked the same question: https://lore.kernel.org/linux-pci/20201120203428.GA272511@bjorn-Precision-5520/ Krzysztof _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23F68C433FE for ; Sun, 6 Dec 2020 20:19:02 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 326F822CF6 for ; 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Sun, 06 Dec 2020 12:16:55 -0800 (PST) Received: from rocinante ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id w11sm12784288pfi.162.2020.12.06.12.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 12:16:54 -0800 (PST) Date: Sun, 6 Dec 2020 21:16:36 +0100 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Bjorn Helgaas Subject: Re: [PATCH v6 1/5] PCI: Unify ECAM constants in native PCI Express drivers Message-ID: References: <20201129230743.3006978-1-kw@linux.com> <20201129230743.3006978-2-kw@linux.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20201129230743.3006978-2-kw@linux.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heiko Stuebner , Shawn Lin , Paul Mackerras , Thomas Petazzoni , Jonathan Chocron , Toan Le , Will Deacon , Rob Herring , Lorenzo Pieralisi , Michal Simek , linux-rockchip@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, Jonathan Derrick , linux-pci@vger.kernel.org, Ray Jui , Florian Fainelli , linux-rpi-kernel@lists.infradead.org, Jonathan Cameron , linux-arm-kernel@lists.infradead.org, Scott Branden , Zhou Wang , Robert Richter , linuxppc-dev@lists.ozlabs.org, Nicolas Saenz Julienne Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Hello Nicolas, Florian and Florian, [...] > -/* Configuration space read/write support */ > -static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) > -{ > - return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) > - | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) > - | (busnr << PCIE_EXT_BUSNUM_SHIFT) > - | (reg & ~3); > -} > - > static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, > int where) > { > @@ -716,7 +704,7 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, > return PCI_SLOT(devfn) ? NULL : base + where; > > /* For devices, write to the config space index register */ > - idx = brcm_pcie_cfg_index(bus->number, devfn, 0); > + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); > writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); > return base + PCIE_EXT_CFG_DATA + where; > } [...] Passing the hard-coded 0 as the "reg" argument here never actually did anything, thus the 32 bit alignment was never correctly enforced. My question would be: should this be 32 bit aligned? It seems like the intention was to perhaps make the alignment? I am sadly not intimately familiar with his hardware, so I am not sure if there is something to fix here or not. Also, I wonder whether it would be safe to pass the offset (the "where" variable) rather than hard-coded 0? Thank you for help in advance! Bjorn also asked the same question: https://lore.kernel.org/linux-pci/20201120203428.GA272511@bjorn-Precision-5520/ Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1DD8C4361B for ; Sun, 6 Dec 2020 20:18:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9FD432310B for ; Sun, 6 Dec 2020 20:18:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9FD432310B Authentication-Results: mail.kernel.org; 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Sun, 06 Dec 2020 12:16:55 -0800 (PST) Received: from rocinante ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id w11sm12784288pfi.162.2020.12.06.12.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 12:16:54 -0800 (PST) Date: Sun, 6 Dec 2020 21:16:36 +0100 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Bjorn Helgaas Subject: Re: [PATCH v6 1/5] PCI: Unify ECAM constants in native PCI Express drivers Message-ID: References: <20201129230743.3006978-1-kw@linux.com> <20201129230743.3006978-2-kw@linux.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201129230743.3006978-2-kw@linux.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201206_151657_659236_EFB66798 X-CRM114-Status: GOOD ( 14.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heiko Stuebner , Benjamin Herrenschmidt , Shawn Lin , Paul Mackerras , Thomas Petazzoni , Jonathan Chocron , Toan Le , Will Deacon , Rob Herring , Lorenzo Pieralisi , Michael Ellerman , Michal Simek , linux-rockchip@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, Jonathan Derrick , linux-pci@vger.kernel.org, Ray Jui , Florian Fainelli , linux-rpi-kernel@lists.infradead.org, Jonathan Cameron , linux-arm-kernel@lists.infradead.org, Scott Branden , Zhou Wang , Robert Richter , linuxppc-dev@lists.ozlabs.org, Nicolas Saenz Julienne Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello Nicolas, Florian and Florian, [...] > -/* Configuration space read/write support */ > -static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) > -{ > - return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) > - | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) > - | (busnr << PCIE_EXT_BUSNUM_SHIFT) > - | (reg & ~3); > -} > - > static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, > int where) > { > @@ -716,7 +704,7 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, > return PCI_SLOT(devfn) ? NULL : base + where; > > /* For devices, write to the config space index register */ > - idx = brcm_pcie_cfg_index(bus->number, devfn, 0); > + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); > writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); > return base + PCIE_EXT_CFG_DATA + where; > } [...] Passing the hard-coded 0 as the "reg" argument here never actually did anything, thus the 32 bit alignment was never correctly enforced. My question would be: should this be 32 bit aligned? It seems like the intention was to perhaps make the alignment? I am sadly not intimately familiar with his hardware, so I am not sure if there is something to fix here or not. Also, I wonder whether it would be safe to pass the offset (the "where" variable) rather than hard-coded 0? Thank you for help in advance! Bjorn also asked the same question: https://lore.kernel.org/linux-pci/20201120203428.GA272511@bjorn-Precision-5520/ Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel