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From: Eric Biggers <ebiggers@kernel.org>
To: Adrian Hunter <adrian.hunter@intel.com>
Cc: linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-fscrypt@vger.kernel.org,
	Satya Tangirala <satyat@google.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Asutosh Das <asutoshd@codeaurora.org>,
	Rob Herring <robh+dt@kernel.org>,
	Neeraj Soni <neersoni@codeaurora.org>,
	Barani Muthukumaran <bmuthuku@codeaurora.org>,
	Peng Zhou <peng.zhou@mediatek.com>,
	Stanley Chu <stanley.chu@mediatek.com>,
	Konrad Dybcio <konradybcio@gmail.com>
Subject: Re: [PATCH v2 3/9] mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors
Date: Thu, 3 Dec 2020 11:23:38 -0800	[thread overview]
Message-ID: <X8k7Oj7e7ARtsmol@gmail.com> (raw)
In-Reply-To: <bf74d785-a88e-f621-24a3-4e68aeeee753@intel.com>

On Thu, Dec 03, 2020 at 08:45:15AM +0200, Adrian Hunter wrote:
> On 3/12/20 4:05 am, Eric Biggers wrote:
> > From: Eric Biggers <ebiggers@google.com>
> > 
> > Move the task descriptor initialization into cqhci_prep_task_desc(), and
> > make it initialize all 128 bits of the task descriptor if the host
> > controller is using 128-bit task descriptors.
> > 
> > This is needed to prepare for CQHCI inline encryption support, which
> > requires 128-bit task descriptors and uses the upper 64 bits.
> > 
> > Note: since some host controllers already enable 128-bit task
> > descriptors, it's unclear why the previous code worked when it wasn't
> > initializing the upper 64 bits.  One possibility is that the bits are
> > being ignored because the features that use them aren't enabled yet.
> > In any case, setting them to 0 won't hurt.
> 
> Coherent allocations are zero-initialized.  So the upper 64-bits stay zero.
> People set 128-bit anyway because the hardware needs it.

Okay, that explains it then -- I didn't realize that dma_alloc_coherent() always
returns zeroed memory.  It isn't mentioned in
Documentation/core-api/dma-api.rst, and there's no kerneldoc comment, so it
wasn't clear.  But apparently it's intentional; see commit 518a2f1925c3
("dma-mapping: zero memory returned from dma_alloc_*").

I'll fix this commit message in the next version.

- Eric

  reply	other threads:[~2020-12-03 19:24 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-03  2:05 [PATCH v2 0/9] eMMC inline encryption support Eric Biggers
2020-12-03  2:05 ` [PATCH v2 1/9] mmc: add basic support for inline encryption Eric Biggers
2020-12-08 23:40   ` Satya Tangirala
2020-12-03  2:05 ` [PATCH v2 2/9] mmc: cqhci: rename cqhci.c to cqhci-core.c Eric Biggers
2020-12-03  2:05 ` [PATCH v2 3/9] mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors Eric Biggers
2020-12-03  6:45   ` Adrian Hunter
2020-12-03 19:23     ` Eric Biggers [this message]
2020-12-08 23:45   ` Satya Tangirala
2020-12-03  2:05 ` [PATCH v2 4/9] mmc: cqhci: add support for inline encryption Eric Biggers
2020-12-03  6:47   ` Adrian Hunter
2020-12-05 10:59   ` Satya Tangirala
2020-12-05 12:33     ` Satya Tangirala
2020-12-05 18:20       ` Eric Biggers
2020-12-05 12:28   ` Satya Tangirala
2020-12-05 18:07     ` Eric Biggers
2020-12-09  0:01       ` Satya Tangirala
2020-12-03  2:05 ` [PATCH v2 5/9] mmc: cqhci: add cqhci_host_ops::program_key Eric Biggers
2020-12-08 23:48   ` Satya Tangirala
2020-12-03  2:05 ` [PATCH v2 6/9] firmware: qcom_scm: update comment for ICE-related functions Eric Biggers
2020-12-08 23:52   ` Satya Tangirala
2020-12-03  2:05 ` [PATCH v2 7/9] dt-bindings: mmc: sdhci-msm: add ICE registers and clock Eric Biggers
2020-12-08 23:54   ` Satya Tangirala
2020-12-03  2:05 ` [PATCH v2 8/9] arm64: dts: qcom: sdm630: add ICE registers and clocks Eric Biggers
2020-12-03  2:05 ` [PATCH v2 9/9] mmc: sdhci-msm: add Inline Crypto Engine support Eric Biggers
2020-12-03  6:51   ` Adrian Hunter
2020-12-05 12:09   ` Satya Tangirala
2020-12-05 19:43     ` Eric Biggers
2020-12-08 23:58       ` Satya Tangirala

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