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[84.1.217.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1740bf48d9sm464218966b.57.2026.07.20.06.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 06:59:27 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: Tvrtko Ursulin , Alex Deucher Cc: amd-gfx@lists.freedesktop.org, Alex Deucher , christian.koenig@amd.com, pierre-eric.pelloux-prayer@amd.com, Natalie Vock Subject: Re: [PATCH 07/11] drm/amdgpu/gfx6: Properly enable/disable priv_req and priv_inst interrupts Date: Mon, 20 Jul 2026 15:59:26 +0200 Message-ID: In-Reply-To: References: <20260713130709.34262-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Thursday, July 16, 2026 4:00:50=E2=80=AFPM Central European Summer Time = Alex=20 > >=20 > > Right, AFAIU assuming the CP hangs, instead of waiting for the TDR > > timeout with this patch it will be instant via drm_sched_fault() called > > from either irq handler. Or if CP does not hang but somehow ends up > > going over it with corruption with this patch it will insta GPU hang. > >=20 > > In any case I think it is needed to have a definitive answer whether the > > interrupts were not enabled until now, and if so, also exercise the > > until now unused code paths just to make sure it all works as expected. > > Presumably there are test cases which trigger both conditions? > >=20 > > Then I would suggest putting this info in the commit message. That is, > > instead of saying "These were used without ever calling get()/put() on > > them." expand with the full story so the whole situation is clear both > > before and after the patch. > >=20 > > Assuming interrupts were not enabled until now, that the unused irq >=20 > > handlers work as expected, and with the improved commit message: > The interrupts would not have been enabled if get() was never called. > I think they were never enabled because radeon didn't implement > support and this code was ported from radeon. > >=20 > > Unless you don't have the hardware to test it and there are no existing > > test cases to verify it? >=20 > An example test would be attempting to access a privileged register > from a user IB. Unfortunately I don't have any test cases like that. We've had some plans f= or=20 writing such test cases and integrating them in IGT but the person who was= =20 going to write them left and since then I haven't managed to get around to = it=20 yet. So I've mainly just used the hang test suite for testing that soft res= et=20 works. If you have doubts about these interrupts on GFX6 then I think we should ju= st=20 drop this patch until we finish those test cases. I still plan to write those test cases but it's really tedious and thankles= s=20 work, so it hasn't been my priority thus far. Best regards, Timur