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[86.58.12.36]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c504a643f12sm127127266b.62.2026.11.10.08.04.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 08:04:47 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Chen-Yu Tsai , Samuel Holland , Maxime Ripard , aiyengar1990@gmail.com Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/2] iommu/sun50i: Don't report TLB prefetch walks as page faults Date: Tue, 10 Nov 2026 17:04:46 +0100 Message-ID: In-Reply-To: <20261110-sun50i-iommu-prefetch-v1-0-43428e792ef6@gmail.com> References: <20261110-sun50i-iommu-prefetch-v1-0-43428e792ef6@gmail.com> X-Mailing-List: iommu@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne torek, 10. november 2026 ob 07:05:16 Srednjeevropski standardni =C4=8Da= s je Arun Iyengar via B4 Relay napisal(a): > On an H616 with a display scanning out, the IOMMU reports page faults > with master -1 at the IOVA right after the end of the framebuffer: once > at the first fbcon frame, and then once per frame for a while after > each TLB flush, e.g. while a video decoder frees its buffers. They are > failed walks of the TLB prefetcher, which the hardware flags with bit 31 > of the page table interrupt registers and no master bit. Patch 1 stops > reporting them. Patch 2 makes the remaining fault messages say which > walk failed and what the interrupt register held. >=20 > Tested on an Orange Pi Zero2 (H616) with HDMI forced on at 1024x768 and > three 4K H.264 decodes through cedrus, on 7.3 kernels with and without > the patches: > - without: 214 "Page fault ... (master -1, dir rd)" lines; > - with: none, no "Page fault" line at all, and no decode errors or > timeouts. > Since the patched kernel prints every fault that is not a masterless > prefetch walk, this also shows that the hardware sets bit 31 for these > walks. =46irst off, display engine isn't in merged yet. Second, I don't observe any such issues with my wip H616 code. I think it's best to wait until driver is merged and can be retested and merged then, if needed. Best regards, Jernej >=20 > These patches were developed with Claude (Anthropic) as a coding > assistant. It investigated the problem and wrote the code and the commit > messages; I reviewed them, and they were tested on an Orange Pi Zero2 > (H616) as described above. >=20 > --- > Arun Iyengar (2): > iommu/sun50i: Don't report TLB prefetches of unmapped pages as faul= ts > iommu/sun50i: Print the page table level and status of a fault >=20 > drivers/iommu/sun50i-iommu.c | 50 ++++++++++++++++++++++++++++++++++----= =2D----- > 1 file changed, 39 insertions(+), 11 deletions(-) > --- > base-commit: 2cf4be57b301ed2d7af82e70cff5dfd96894d8de > change-id: 20261110-sun50i-iommu-prefetch-85cc9ecff559 >=20 > Best regards, > -- =20 > Arun Iyengar >=20 >=20 >=20