diff for duplicates of <Y/6CgMvoRciA7Ow1@spud>

diff --git a/N1/1.1.hdr b/N1/1.1.hdr
new file mode 100644
index 0000000..5a32186
--- /dev/null
+++ b/N1/1.1.hdr
@@ -0,0 +1,3 @@
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diff --git a/a/1.txt b/N1/1.1.txt
similarity index 68%
rename from a/1.txt
rename to N1/1.1.txt
index 6e07659..6d95a48 100644
--- a/a/1.txt
+++ b/N1/1.1.txt
@@ -5,7 +5,7 @@ On Fri, Feb 24, 2023 at 05:01:06PM +0000, Andy Chiu wrote:
 > riscv_v_vsize to save the size of all the vector registers. It assumes all
 > harts has the same capabilities in a SMP system.
 > 
-> [guoren at linux.alibaba.com: add has_vector checking]
+> [guoren@linux.alibaba.com: add has_vector checking]
 > Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
 > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
 > Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
@@ -17,11 +17,3 @@ Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
 
 Thanks,
 Conor.
-
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diff --git a/N1/2.txt b/N1/2.txt
new file mode 100644
index 0000000..e409076
--- /dev/null
+++ b/N1/2.txt
@@ -0,0 +1,4 @@
+_______________________________________________
+linux-riscv mailing list
+linux-riscv@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/a/content_digest b/N1/content_digest
index 4326446..92c15c6 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,10 +1,32 @@
  "ref\020230224170118.16766-1-andy.chiu@sifive.com\0"
  "ref\020230224170118.16766-8-andy.chiu@sifive.com\0"
  "From\0Conor Dooley <conor@kernel.org>\0"
- "Subject\0[PATCH -next v14 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context\0"
- "Date\0Tue, 28 Feb 2023 22:39:07 -0000\0"
- "To\0kvm-riscv@lists.infradead.org\0"
- "\00:1\0"
+ "Subject\0Re: [PATCH -next v14 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context\0"
+ "Date\0Tue, 28 Feb 2023 22:38:56 +0000\0"
+ "To\0Andy Chiu <andy.chiu@sifive.com>\0"
+ "Cc\0linux-riscv@lists.infradead.org"
+  palmer@dabbelt.com
+  anup@brainfault.org
+  atishp@atishpatra.org
+  kvm-riscv@lists.infradead.org
+  kvm@vger.kernel.org
+  vineetg@rivosinc.com
+  greentime.hu@sifive.com
+  guoren@linux.alibaba.com
+  Vincent Chen <vincent.chen@sifive.com>
+  Paul Walmsley <paul.walmsley@sifive.com>
+  Albert Ou <aou@eecs.berkeley.edu>
+  Guo Ren <guoren@kernel.org>
+  Heiko Stuebner <heiko@sntech.de>
+  Changbin Du <changbin.du@intel.com>
+  Masahiro Yamada <masahiroy@kernel.org>
+  Li Zhengyu <lizhengyu3@huawei.com>
+  Conor Dooley <conor.dooley@microchip.com>
+  Andrew Jones <ajones@ventanamicro.com>
+  Jisheng Zhang <jszhang@kernel.org>
+  Tsukasa OI <research_trasio@irq.a4lg.com>
+ " Richard Henderson <richard.henderson@linaro.org>\0"
+ "\02:1.1\0"
  "b\0"
  "On Fri, Feb 24, 2023 at 05:01:06PM +0000, Andy Chiu wrote:\n"
  "> From: Greentime Hu <greentime.hu@sifive.com>\n"
@@ -13,7 +35,7 @@
  "> riscv_v_vsize to save the size of all the vector registers. It assumes all\n"
  "> harts has the same capabilities in a SMP system.\n"
  "> \n"
- "> [guoren at linux.alibaba.com: add has_vector checking]\n"
+ "> [guoren@linux.alibaba.com: add has_vector checking]\n"
  "> Co-developed-by: Guo Ren <guoren@linux.alibaba.com>\n"
  "> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>\n"
  "> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>\n"
@@ -24,14 +46,22 @@
  "Reviewed-by: Conor Dooley <conor.dooley@microchip.com>\n"
  "\n"
  "Thanks,\n"
- "Conor.\n"
+ Conor.
+ "\02:1.2\0"
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+ "_______________________________________________\n"
+ "linux-riscv mailing list\n"
+ "linux-riscv@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-riscv
 
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