[GIT PULL] x86/cpu for v6.3-rc1

[Borislav Petkov <bp@alien8.de>]

Hi Linus,

please pull the currently accumulated x86/cpu pile for 6.3.

There are a bunch of easy peasy merge conflicts, an exemplary resolve of
which I'm adding at the end of this message.

Thx.

---

The following changes since commit b7bfaa761d760e72a969d116517eaa12e404c262:

  Linux 6.2-rc3 (2023-01-08 11:49:43 -0600)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git tags/x86_cpu_for_v6.3_rc1

for you to fetch changes up to 7914695743d598b189d549f2f57af24aa5633705:

  x86/amd: Cache debug register values in percpu variables (2023-01-31 20:09:26 +0100)

----------------------------------------------------------------
- Cache the AMD debug registers in per-CPU variables to avoid MSR writes
  where possible, when supporting a debug registers swap feature for
  SEV-ES guests

- Add support for AMD's version of eIBRS called Automatic IBRS which is
  a set-and-forget control of indirect branch restriction speculation
  resources on privilege change

- Add support for a new x86 instruction - LKGS - Load kernel GS which is
  part of the FRED infrastructure

- Reset SPEC_CTRL upon init to accomodate use cases like kexec which
  rediscover

- Other smaller fixes and cleanups

----------------------------------------------------------------
Alexey Kardashevskiy (1):
      x86/amd: Cache debug register values in percpu variables

Ashok Raj (1):
      x86/cpu: Remove redundant extern x86_read_arch_cap_msr()

Breno Leitao (1):
      x86/bugs: Reset speculation control settings on init

H. Peter Anvin (Intel) (5):
      x86/cpufeature: Add the CPU feature bit for LKGS
      x86/opcode: Add the LKGS instruction to x86-opcode-map
      x86/gsseg: Make asm_load_gs_index() take an u16
      x86/gsseg: Move load_gs_index() to its own new header file
      x86/gsseg: Use the LKGS instruction if available for load_gs_index()

Ingo Molnar (1):
      x86/gsseg: Add the new <asm/gsseg.h> header to <asm/asm-prototypes.h>

Kim Phillips (8):
      x86/cpu, kvm: Add support for CPUID_80000021_EAX
      KVM: x86: Move open-coded CPUID leaf 0x80000021 EAX bit propagation code
      x86/cpu, kvm: Add the NO_NESTED_DATA_BP feature
      x86/cpu, kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf
      x86/cpu, kvm: Add the Null Selector Clears Base feature
      x86/cpu, kvm: Add the SMM_CTL MSR not present feature
      x86/cpu: Support AMD Automatic IBRS
      KVM: x86: Propagate the AMD Automatic IBRS feature to the guest

 Documentation/admin-guide/hw-vuln/spectre.rst   |  6 +--
 Documentation/admin-guide/kernel-parameters.txt |  6 +--
 arch/x86/entry/entry_64.S                       |  2 +-
 arch/x86/include/asm/asm-prototypes.h           |  1 +
 arch/x86/include/asm/cpufeature.h               |  7 ++-
 arch/x86/include/asm/cpufeatures.h              | 12 ++++-
 arch/x86/include/asm/debugreg.h                 |  9 +++-
 arch/x86/include/asm/disabled-features.h        |  3 +-
 arch/x86/include/asm/gsseg.h                    | 66 +++++++++++++++++++++++++
 arch/x86/include/asm/mmu_context.h              |  1 +
 arch/x86/include/asm/msr-index.h                |  6 +++
 arch/x86/include/asm/required-features.h        |  3 +-
 arch/x86/include/asm/special_insns.h            | 21 --------
 arch/x86/kernel/cpu/amd.c                       | 49 ++++++++++++------
 arch/x86/kernel/cpu/bugs.c                      | 31 ++++++++----
 arch/x86/kernel/cpu/common.c                    | 27 +++++-----
 arch/x86/kernel/cpu/cpu.h                       |  2 -
 arch/x86/kernel/cpu/tsx.c                       |  1 +
 arch/x86/kernel/hw_breakpoint.c                 |  4 +-
 arch/x86/kernel/paravirt.c                      |  1 +
 arch/x86/kernel/signal_32.c                     |  1 +
 arch/x86/kernel/tls.c                           |  1 +
 arch/x86/kvm/cpuid.c                            | 41 ++++++++-------
 arch/x86/kvm/reverse_cpuid.h                    |  1 +
 arch/x86/kvm/svm/svm.c                          |  3 ++
 arch/x86/kvm/x86.c                              |  3 ++
 arch/x86/lib/x86-opcode-map.txt                 |  1 +
 arch/x86/xen/enlighten_pv.c                     |  1 +
 tools/arch/x86/include/asm/cpufeatures.h        |  1 +
 tools/arch/x86/lib/x86-opcode-map.txt           |  1 +
 30 files changed, 218 insertions(+), 94 deletions(-)
 create mode 100644 arch/x86/include/asm/gsseg.h

 ---

 merge conflicts resolve:

 ---

diff --cc arch/x86/include/asm/cpufeatures.h
index 49973061b5bd,06909dc7fa63..389ea336258f
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -314,7 -312,7 +314,8 @@@
  #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
  #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
  #define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* "" CMPccXADD instructions */
 +#define X86_FEATURE_ARCH_PERFMON_EXT	(12*32+ 8) /* "" Intel Architectural PerfMon Extension */
+ #define X86_FEATURE_LKGS		(12*32+18) /* "" Load "kernel" (userspace) GS */
  #define X86_FEATURE_AMX_FP16		(12*32+21) /* "" AMX fp16 Support */
  #define X86_FEATURE_AVX_IFMA            (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
  
diff --cc arch/x86/include/asm/special_insns.h
index f358a23f228d,cfd9499b617c..de48d1389936
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@@ -184,19 -173,9 +173,9 @@@ static __always_inline void wbinvd(void
  	native_wbinvd();
  }
  
- 
- static inline void load_gs_index(unsigned int selector)
- {
- #ifdef CONFIG_X86_64
- 	native_load_gs_index(selector);
- #else
- 	loadsegment(gs, selector);
- #endif
- }
- 
  #endif /* CONFIG_PARAVIRT_XXL */
  
 -static inline void clflush(volatile void *__p)
 +static __always_inline void clflush(volatile void *__p)
  {
  	asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
  }
diff --cc arch/x86/kernel/cpu/common.c
index 65ceabb2e114,62c73c57f16d..a394bbba7a4b
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@@ -1403,14 -1412,6 +1414,9 @@@ static void __init cpu_set_bug_bits(str
  			setup_force_cpu_bug(X86_BUG_RETBLEED);
  	}
  
- 	if (cpu_has(c, X86_FEATURE_IBRS_ENHANCED) &&
- 	    !cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
- 	    !(ia32_cap & ARCH_CAP_PBRSB_NO))
- 		setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
- 
 +	if (cpu_matches(cpu_vuln_blacklist, SMT_RSB))
 +		setup_force_cpu_bug(X86_BUG_SMT_RSB);
 +
  	if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
  		return;
  

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette