From: William Breathitt Gray <william.gray@linaro.org>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Mark Brown <broonie@kernel.org>,
Aidan MacDonald <aidanmacdonald.0x0@gmail.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/1] regmap-irq: Place kernel doc of struct regmap_irq_chip in order
Date: Wed, 22 Feb 2023 11:43:28 -0500 [thread overview]
Message-ID: <Y/ZGMDI9wcOwMUWI@fedora> (raw)
In-Reply-To: <20230220153334.87049-1-andriy.shevchenko@linux.intel.com>
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On Mon, Feb 20, 2023 at 05:33:34PM +0200, Andy Shevchenko wrote:
> It seems that a couple of members got lost theirorder, put them back.
Looks like a typographical error here: "theirorder".
> Besides that, split field descriptions into groups in the same way
> as it's done in the structure definition.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> v2: rebased on the latest Linux Next (Mark)
> include/linux/regmap.h | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/include/linux/regmap.h b/include/linux/regmap.h
> index 4d10790adeb0..1c777566fb7d 100644
> --- a/include/linux/regmap.h
> +++ b/include/linux/regmap.h
> @@ -1551,6 +1551,7 @@ struct regmap_irq_chip_data;
> * @use_ack: Use @ack register even if it is zero.
> * @ack_invert: Inverted ack register: cleared bits for ack.
> * @clear_ack: Use this to set 1 and 0 or vice-versa to clear interrupts.
> + * @status_invert: Inverted status register: cleared bits are active interrupts.
> * @wake_invert: Inverted wake register: cleared bits are wake enabled.
> * @type_in_mask: Use the mask registers for controlling irq type. Use this if
> * the hardware provides separate bits for rising/falling edge
> @@ -1560,18 +1561,19 @@ struct regmap_irq_chip_data;
> * @clear_on_unmask: For chips with interrupts cleared on read: read the status
> * registers before unmasking interrupts to clear any bits
> * set when they were masked.
> + * @runtime_pm: Hold a runtime PM lock on the device when accessing it.
> * @not_fixed_stride: Used when chip peripherals are not laid out with fixed
> * stride. Must be used with sub_reg_offsets containing the
> * offsets to each peripheral. Deprecated; the same thing
> * can be accomplished with a @get_irq_reg callback, without
> * the need for a @sub_reg_offsets table.
> - * @status_invert: Inverted status register: cleared bits are active interrupts.
> - * @runtime_pm: Hold a runtime PM lock on the device when accessing it.
> *
> * @num_regs: Number of registers in each control bank.
> + *
> * @irqs: Descriptors for individual IRQs. Interrupt numbers are
> * assigned based on the index in the array of the interrupt.
> * @num_irqs: Number of descriptors.
> + *
> * @num_type_reg: Number of type registers. Deprecated, use config registers
> * instead.
> * @num_virt_regs: Number of non-standard irq configuration registers.
> @@ -1579,6 +1581,7 @@ struct regmap_irq_chip_data;
> * instead.
> * @num_config_bases: Number of config base registers.
> * @num_config_regs: Number of config registers for each config base register.
> + *
> * @handle_pre_irq: Driver specific callback to handle interrupt from device
> * before regmap_irq_handler process the interrupts.
> * @handle_post_irq: Driver specific callback to handle interrupt from device
> @@ -1625,12 +1628,12 @@ struct regmap_irq_chip {
> unsigned int use_ack:1;
> unsigned int ack_invert:1;
> unsigned int clear_ack:1;
> + unsigned int status_invert:1;
> unsigned int wake_invert:1;
> - unsigned int runtime_pm:1;
> unsigned int type_in_mask:1;
> unsigned int clear_on_unmask:1;
> + unsigned int runtime_pm:1;
> unsigned int not_fixed_stride:1;
> - unsigned int status_invert:1;
These don't look alphabetical, so what is the order for these?
William Breathitt Gray
>
> int num_regs;
>
> --
> 2.39.1
>
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next prev parent reply other threads:[~2023-02-23 15:59 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-20 15:33 [PATCH v2 1/1] regmap-irq: Place kernel doc of struct regmap_irq_chip in order Andy Shevchenko
2023-02-22 16:43 ` William Breathitt Gray [this message]
2023-02-23 18:52 ` Andy Shevchenko
2023-02-22 17:46 ` William Breathitt Gray
2023-02-24 15:01 ` Andy Shevchenko
2023-02-22 19:24 ` William Breathitt Gray
2023-02-24 16:36 ` Andy Shevchenko
2023-03-06 14:09 ` Mark Brown
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