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[34.78.232.44]) by smtp.gmail.com with ESMTPSA id m11-20020a5d6a0b000000b002c558228b6dsm1459443wru.12.2023.02.16.05.09.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 05:09:38 -0800 (PST) Date: Thu, 16 Feb 2023 13:09:33 +0000 From: Mostafa Saleh To: Eric Auger Cc: qemu-devel@nongnu.org, jean-philippe@linaro.org, peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: Re: [RFC PATCH 05/16] hw/arm/smmuv3: Add page table walk for stage-2 Message-ID: References: <20230205094411.793816-1-smostafa@google.com> <20230205094411.793816-6-smostafa@google.com> <4e248ff8-3032-0697-d50c-d3b62b072a82@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4e248ff8-3032-0697-d50c-d3b62b072a82@redhat.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=smostafa@google.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: fb8iy5y1ZGbM Hi Eric, On Wed, Feb 15, 2023 at 05:52:39PM +0100, Eric Auger wrote: > > In preparation for adding stage-2 support. Add Stage-2 PTW code. > > Only Aarch64 fromat is supported as stage-1. > format I will update it. > > + uint64_t subpage_size = 1ULL << level_shift(level, granule_sz); > > + uint64_t mask = subpage_size - 1; > > + uint32_t offset = iova_level_offset(iova, inputsize, level, granule_sz); > > + uint64_t pte, gpa; > > + dma_addr_t pte_addr = baseaddr + offset * sizeof(pte); > > + uint8_t ap; > > + > > + if (get_pte(baseaddr, offset, &pte, info)) { > > + goto error; > > + } > > + trace_smmu_ptw_level(level, iova, subpage_size, > > + baseaddr, offset, pte); > I can the trace point names should be updated as well (and > differentiated between S1/S2) I was thinking we could leave those with stage argument, and only update trace_smmu_ptw_level to have stage argument as the others. > > + if (is_permission_fault_s2(ap, perm)) { > > + info->type = SMMU_PTW_ERR_PERMISSION; > don't we have to different S1 versus S2 faults? Yes, I missed that, I see setting info->u.f_walk_eabt.s2 should be enough, this will set the S2 field in the fault event. > > int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, > > SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) > > { > > - if (!cfg->aa64) { > > - /* > > - * This code path is not entered as we check this while decoding > > - * the configuration data in the derived SMMU model. > > - */ > > - g_assert_not_reached(); > if that's still true for S2, maybe keep that check here upfront? Stage-2 is checked in STE parsing and throws BAD_STE if not aa64, which I believe is not correct, however I think we can just call g_assert_not_reached() during STE parsing, I don’t see added value for saving this field in SMMUTransCfg if we don’t use it. I am not sure why this check exists for stage-1 as it is hardcoded in decode_cd anyway. > > +{ > > + uint64_t ret; > > + /* > > + * Get the number of bits handled by next levels, then any extra bits in > > + * the address should index the concatenated tables. This relation can > > + * deduced from tables in ARM ARM: D8.2.7-9 > > + */ > > + int shift = (SMMU_MAX_LEVELS - start_level) * (granule - 3) + granule; > can't we factorize anything with the S1 PTW? > indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; Yes, I think we can refactor some of these in common functions/macros, I will do that in v2. > > @@ -28,6 +28,7 @@ > > #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) > > > > #define SMMU_MAX_VA_BITS 48 > > +#define SMMU_MAX_LEVELS 4 > can't this be reused as well with S1 PTW? I believe yes, I will update it. Thanks, Mostafa