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[34.78.232.44]) by smtp.gmail.com with ESMTPSA id r128-20020a1c2b86000000b003dff2b493c8sm5602673wmr.36.2023.02.16.05.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 05:20:22 -0800 (PST) Date: Thu, 16 Feb 2023 13:20:16 +0000 From: Mostafa Saleh To: Eric Auger Cc: qemu-devel@nongnu.org, jean-philippe@linaro.org, peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: Re: [RFC PATCH 07/16] hw/arm/smmuv3: Check validity of stage-2 page table Message-ID: References: <20230205094411.793816-1-smostafa@google.com> <20230205094411.793816-8-smostafa@google.com> <8a051757-8452-5c69-b929-576f8c93e887@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8a051757-8452-5c69-b929-576f8c93e887@redhat.com> Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=smostafa@google.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: 46MEbEkPqkhW Hi Eric, > > can have a valid page table as described in ARM ARM D8.2 Translation > > process. > > The idea is to see for the highest possible number of IPA bits, how > > many concatenated tables we would need, if it is more than 16, then > > this is not possible. > > This rather checks the validity and consistency of the STE S2 fields. > The patch title sounds a bit misleading to me. I will update the wording. > > +static bool s2_pgtable_config_valid(uint8_t sl0, uint8_t t0sz, uint8_t gran) > > +{ > > + int level = get_start_level(sl0, gran); > > + uint64_t ia_bits = 64 - t0sz; > s/ia/ipa I will update it. > > + uint64_t mx = (1ULL << ia_bits) - 1; > s/mx/max_ipa I will update it. > > > > + if (!s2_pgtable_config_valid(cfg->s2cfg.sl0, cfg->s2cfg.tsz, > > + cfg->s2cfg.granule_sz)) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "SMMUv3 STE stage 2 config not valid!\n"); > > + goto bad_ste; > > + } > > + > To me this would need to be integrated into the STE decoding patch. This > latter shall be self-contained if possible to ease the review I will squash it, I was trying to keep patches small, but it makes sense to validate STE in the same patch parsing it. Thanks, Mostafa