diff for duplicates of <Y+PnorGskAAIsODw@spud>

diff --git a/N1/1.1.hdr b/N1/1.1.hdr
new file mode 100644
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diff --git a/a/1.txt b/N1/1.1.txt
similarity index 78%
rename from a/1.txt
rename to N1/1.1.txt
index 7faf605..5c10777 100644
--- a/a/1.txt
+++ b/N1/1.1.txt
@@ -22,22 +22,14 @@ On Mon, Jan 30, 2023 at 08:13:20AM +0000, Conor Dooley wrote:
 
 Palmer replied there today with his rationale & an expectation that we
 do the same thing for vector as we did for float:
-https://lore.kernel.org/linux-riscv/mhng-4c71ada6-003c-414f-9a74-efa3ccd2856b at palmer-ri-x1c9/T/#m366779709bbcf7672b5277b3bb27a7d6ce6c6115
+https://lore.kernel.org/linux-riscv/mhng-4c71ada6-003c-414f-9a74-efa3ccd2856b@palmer-ri-x1c9/T/#m366779709bbcf7672b5277b3bb27a7d6ce6c6115
 
 > 
 > And I suppose, it never got any further attention as it isn't needed by
 > any in-tree code?
 > 
-> > [1]https://lore.kernel.org/all/CAOnJCULtT-y9vo6YhW7bW9XyKRdod-hvFfr02jHVamR_LcsKdA at mail.gmail.com/
-> > [2]https://lore.kernel.org/all/20221216185012.2342675-1-abdulras at google.com/
+> > [1]https://lore.kernel.org/all/CAOnJCULtT-y9vo6YhW7bW9XyKRdod-hvFfr02jHVamR_LcsKdA@mail.gmail.com/
+> > [2]https://lore.kernel.org/all/20221216185012.2342675-1-abdulras@google.com/
 
 Cheers,
 Conor.
-
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diff --git a/N1/2.hdr b/N1/2.hdr
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diff --git a/N1/2.txt b/N1/2.txt
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index 0000000..e409076
--- /dev/null
+++ b/N1/2.txt
@@ -0,0 +1,4 @@
+_______________________________________________
+linux-riscv mailing list
+linux-riscv@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/a/content_digest b/N1/content_digest
index b2da48b..31dce01 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -4,10 +4,22 @@
  "ref\0CABgGipW430Cs0OgYO94RqfwrBFJOPV3HeS24Rv3nHgr4yOVaPQ@mail.gmail.com\0"
  "ref\0Y9d8IBqXyep+PJTq@wendy\0"
  "From\0Conor Dooley <conor@kernel.org>\0"
- "Subject\0[PATCH -next v13 19/19] riscv: Enable Vector code to be built\0"
- "Date\0Wed, 08 Feb 2023 18:19:23 -0000\0"
- "To\0kvm-riscv@lists.infradead.org\0"
- "\00:1\0"
+ "Subject\0Re: [PATCH -next v13 19/19] riscv: Enable Vector code to be built\0"
+ "Date\0Wed, 8 Feb 2023 18:19:14 +0000\0"
+ "To\0Conor Dooley <conor.dooley@microchip.com>\0"
+ "Cc\0Andy Chiu <andy.chiu@sifive.com>"
+  linux-riscv@lists.infradead.org
+  palmer@dabbelt.com
+  anup@brainfault.org
+  atishp@atishpatra.org
+  kvm-riscv@lists.infradead.org
+  kvm@vger.kernel.org
+  vineetg@rivosinc.com
+  greentime.hu@sifive.com
+  guoren@linux.alibaba.com
+  Paul Walmsley <paul.walmsley@sifive.com>
+ " Albert Ou <aou@eecs.berkeley.edu>\0"
+ "\02:1.1\0"
  "b\0"
  "Hey Andy,\n"
  "\n"
@@ -33,24 +45,32 @@
  "\n"
  "Palmer replied there today with his rationale & an expectation that we\n"
  "do the same thing for vector as we did for float:\n"
- "https://lore.kernel.org/linux-riscv/mhng-4c71ada6-003c-414f-9a74-efa3ccd2856b at palmer-ri-x1c9/T/#m366779709bbcf7672b5277b3bb27a7d6ce6c6115\n"
+ "https://lore.kernel.org/linux-riscv/mhng-4c71ada6-003c-414f-9a74-efa3ccd2856b@palmer-ri-x1c9/T/#m366779709bbcf7672b5277b3bb27a7d6ce6c6115\n"
  "\n"
  "> \n"
  "> And I suppose, it never got any further attention as it isn't needed by\n"
  "> any in-tree code?\n"
  "> \n"
- "> > [1]https://lore.kernel.org/all/CAOnJCULtT-y9vo6YhW7bW9XyKRdod-hvFfr02jHVamR_LcsKdA at mail.gmail.com/\n"
- "> > [2]https://lore.kernel.org/all/20221216185012.2342675-1-abdulras at google.com/\n"
+ "> > [1]https://lore.kernel.org/all/CAOnJCULtT-y9vo6YhW7bW9XyKRdod-hvFfr02jHVamR_LcsKdA@mail.gmail.com/\n"
+ "> > [2]https://lore.kernel.org/all/20221216185012.2342675-1-abdulras@google.com/\n"
  "\n"
  "Cheers,\n"
- "Conor.\n"
+ Conor.
+ "\02:1.2\0"
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+ "\01:2\0"
+ "b\0"
+ "_______________________________________________\n"
+ "linux-riscv mailing list\n"
+ "linux-riscv@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-riscv
 
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