From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Simon Glass <sjg@chromium.org>
Cc: <u-boot@lists.denx.de>, <ycliang@andestech.com>, <rick@andestech.com>
Subject: Re: [RFC PATCH] doc: arch: Add document for RISC-V architecture
Date: Mon, 13 Feb 2023 11:01:46 +0000 [thread overview]
Message-ID: <Y+oYmgRgbLdRSNPM@APC323> (raw)
In-Reply-To: <CAPnjgZ0H0_+2=O9H7PJQxTvXLT4LPzxni7vrTzXMURUp=VZcvQ@mail.gmail.com>
On Sun, Feb 12, 2023 at 12:25:56PM -0700, Simon Glass wrote:
> On Sun, 12 Feb 2023 at 00:01, Yu Chien Peter Lin <peterlin@andestech.com> wrote:
> >
> > This patch adds a brief introduction to the RISC-V architecture and
> > the typical boot process used on a variety of RISC-V platforms.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > ---
> > Hi RISC-V community,
> >
> > Please leave a comment if there is anything I've missed that should
> > be mentioned in the document. Thanks.
> > ---
> > doc/arch/index.rst | 1 +
> > doc/arch/riscv.rst | 43 +++++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 44 insertions(+)
> > create mode 100644 doc/arch/riscv.rst
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> Looks good. One nit is that we try to talk in terms of boot 'phases'
> rather than stages.
Hi Simon,
Thanks for the review, I'll update in the next patch.
Best regards,
Peter Lin
> Regards,
> Simon
next prev parent reply other threads:[~2023-02-13 3:06 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-12 7:00 [RFC PATCH] doc: arch: Add document for RISC-V architecture Yu Chien Peter Lin
2023-02-12 17:16 ` Samuel Holland
2023-02-12 19:25 ` Simon Glass
2023-02-13 11:01 ` Yu-Chien Peter Lin [this message]
2023-02-13 7:36 ` Heinrich Schuchardt
2023-02-14 11:28 ` Yu-Chien Peter Lin
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