From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 2/2] clk: renesas: r8a779f0: Add SASYNCPER internal clock
Date: Wed, 12 Oct 2022 20:50:57 +0200 [thread overview]
Message-ID: <Y0cMkfXOMWySUurL@shikoro> (raw)
In-Reply-To: <18e6765bfc3bf7c3ee5ce93a370d377c1d17728e.1665558014.git.geert+renesas@glider.be>
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On Wed, Oct 12, 2022 at 09:02:34AM +0200, Geert Uytterhoeven wrote:
> Add the SASYNCPER internal clock, which is the clock source of the
> various SASYNCPERD[124] clocks, to match the clock tree diagram in the
> documentation.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
As discussed, looks good!
Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
For the record, I'd like to test as well, but that will need some more
days until the board shows up in a lab again.
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prev parent reply other threads:[~2022-10-12 18:51 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-12 7:02 [PATCH 0/2] clk: renesas: r8a779f0: Minor fixes Geert Uytterhoeven
2022-10-12 7:02 ` [PATCH 1/2] clk: renesas: r8a779f0: Fix SD0H clock name Geert Uytterhoeven
2022-10-12 18:48 ` Wolfram Sang
2022-10-12 7:02 ` [PATCH 2/2] clk: renesas: r8a779f0: Add SASYNCPER internal clock Geert Uytterhoeven
2022-10-12 18:50 ` Wolfram Sang [this message]
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