Re: [PATCH] RISC-V: Add support for the zicbom extension

[Conor Dooley <conor@kernel.org>]

On Fri, Aug 12, 2022 at 09:25:23AM +0100, Conor Dooley wrote:
> On Wed, Aug 10, 2022 at 08:31:38PM -0700, Palmer Dabbelt wrote:
> > This was recently added to binutils and with any luck will soon be in
> > Linux, without it sparse will fail when trying to build new kernels on
> > systems with new toolchains.
> > 
> 
> In passing while testing the zihintpause one:
> Tested-by: Conor Dooley <conor.dooley@microchip.com>

Hey Luc,
Would you be able to take a look at this patch and at
https://lore.kernel.org/linux-sparse/YvYQSdQBuZGSit2s@wendy/T/#t
please? They're causing sparse to fail for recent kernels when the
extensions are used.

Thanks,
Conor.

> 
> > Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> > ---
> >  target-riscv.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/target-riscv.c b/target-riscv.c
> > index 217ab7e8..db0f7e57 100644
> > --- a/target-riscv.c
> > +++ b/target-riscv.c
> > @@ -19,6 +19,7 @@
> >  #define RISCV_GENERIC	(RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU)
> >  #define RISCV_ZICSR	(1 << 10)
> >  #define RISCV_ZIFENCEI	(1 << 11)
> > +#define RISCV_ZICBOM	(1 << 12)
> >  
> >  static unsigned int riscv_flags;
> >  
> > @@ -41,6 +42,7 @@ static void parse_march_riscv(const char *arg)
> >  		{ "c",		RISCV_COMP },
> >  		{ "_zicsr",	RISCV_ZICSR },
> >  		{ "_zifencei",	RISCV_ZIFENCEI },
> > +		{ "_zicbom",	RISCV_ZICBOM },
> >  	};
> >  	int i;
> >  
> > @@ -131,6 +133,8 @@ static void predefine_riscv(const struct target *self)
> >  		predefine("__riscv_zicsr", 1, "1");
> >  	if (riscv_flags & RISCV_ZIFENCEI)
> >  		predefine("__riscv_zifencei", 1, "1");
> > +	if (riscv_flags & RISCV_ZICBOM)
> > +		predefine("__riscv_zicbom", 1, "1");
> >  
> >  	if (cmodel)
> >  		predefine_strong("__riscv_cmodel_%s", cmodel);
> > -- 
> > 2.34.1
> > 
>