From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6753BC433FE for ; Thu, 13 Oct 2022 10:36:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229454AbiJMKgf (ORCPT ); Thu, 13 Oct 2022 06:36:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229548AbiJMKge (ORCPT ); Thu, 13 Oct 2022 06:36:34 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3928E52CC for ; Thu, 13 Oct 2022 03:36:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665657393; x=1697193393; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=84cm2nDkKB3FojEUx+eiD5IfKY7NpFQn3U+ONC/nHWs=; b=liCNlSJYDFjtDJG/QLl641ERRjE2fACjYyUUocGgb9+Z55OElA3LUDP2 JG5QLSUh7vXKleQDTVzECTSZ8dPrn4pgm3+B0JjkCqjWjgalDPuUi7e47 bmi4VbVfV+YEaJG6p8wC93NS8rloF1v2bUtTTk/y1lyeHnwZs7G+TeI73 4aSQusX+O8ZRfnXMDK+BPpFLUeLWLJnGKcocDf6Z61QuTZapaeVzob/Ec /HPfURJSG/goD09FCAdYIm7g7s3Ei8OUGH8TDflw4ROI+Xj9lswt3JgCa bj8cqDk3gFkdj8F685YQ8kQHU/cHjXsxAsDTGtPb8/ImykO3QLFDfk9eE g==; X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="305034182" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="305034182" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 03:36:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="872275679" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="872275679" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.191]) by fmsmga006.fm.intel.com with SMTP; 13 Oct 2022 03:36:30 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Oct 2022 13:36:30 +0300 Date: Thu, 13 Oct 2022 13:36:30 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Thomas Zimmermann Cc: Jocelyn Falempe , dri-devel@lists.freedesktop.org, airlied@redhat.com, michel@daenzer.net, stable@vger.kernel.org Subject: Re: [PATCH] drm/mgag200: Fix PLL setup for G200_SE_A rev >=4 Message-ID: References: <20221013082901.471417-1-jfalempe@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Patchwork-Hint: comment Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Thu, Oct 13, 2022 at 11:05:19AM +0200, Thomas Zimmermann wrote: > Hi > > Am 13.10.22 um 10:29 schrieb Jocelyn Falempe: > > For G200_SE_A, PLL M setting is wrong, which leads to blank screen, > > or "signal out of range" on VGA display. > > previous code had "m |= 0x80" which was changed to > > m |= ((pixpllcn & BIT(8)) >> 1); > > > > Tested on G200_SE_A rev 42 > > > > This line of code was moved to another file with > > commit 85397f6bc4ff ("drm/mgag200: Initialize each model in separate > > function") but can be easily backported before this commit. > > > > Fixes: 2dd040946ecf ("drm/mgag200: Store values (not bits) in struct mgag200_pll_values") > > Cc: stable@vger.kernel.org > > Signed-off-by: Jocelyn Falempe > > --- > > drivers/gpu/drm/mgag200/mgag200_g200se.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/mgag200/mgag200_g200se.c b/drivers/gpu/drm/mgag200/mgag200_g200se.c > > index be389ed91cbd..4ec035029b8b 100644 > > --- a/drivers/gpu/drm/mgag200/mgag200_g200se.c > > +++ b/drivers/gpu/drm/mgag200/mgag200_g200se.c > > @@ -284,7 +284,7 @@ static void mgag200_g200se_04_pixpllc_atomic_update(struct drm_crtc *crtc, > > pixpllcp = pixpllc->p - 1; > > pixpllcs = pixpllc->s; > > > > - xpixpllcm = pixpllcm | ((pixpllcn & BIT(8)) >> 1); > > + xpixpllcm = pixpllcm | BIT(7); > > Thanks for figuring this out. G200SE apparently is special compared to > the other models. The old MGA docs only list this bit as . > Really makes me wonder why this is different. Could measure eg. the vblank interval with and without that bit set and see what effect it has. Assuming the PLL locks without the bit of course. -- Ville Syrjälä Intel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6DFCC4332F for ; Thu, 13 Oct 2022 10:36:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A482A10E212; Thu, 13 Oct 2022 10:36:39 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 59B0410E212 for ; Thu, 13 Oct 2022 10:36:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665657394; x=1697193394; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=84cm2nDkKB3FojEUx+eiD5IfKY7NpFQn3U+ONC/nHWs=; b=Xo4srt8Sc+4DuEDjqdcjzvRZYIMub112Zp7zlOKfNII7J9kVYMVGNn2X 4rkFpuoN+YSC0vX1DrgXU2xvrbchCeYrXDC8iOHtx1RBrhAKCAYAVaZfe N1qbVApQXM4fU3JSXVciAlxJpvzx8LQD8onRo8uzxWm5H/iFoe3rMQF/9 DwNCQB7ZVEym6+h71Gqan/14ho5NCIEhquVVdV8Ezs9XMkKW8dNzRB+lC LRdZXV98GJkH4k4fAL6RrSOoi1SJ6/o7qrwYKlH3QompkNB9xvEd/TUzk i0qGXaEv3StnvS9mpYnt0ELQ4K3EIor5VhwmF5EcYWu9q0ZkzDE5CCxCA Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="391350427" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="391350427" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 03:36:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="872275679" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="872275679" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.191]) by fmsmga006.fm.intel.com with SMTP; 13 Oct 2022 03:36:30 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Oct 2022 13:36:30 +0300 Date: Thu, 13 Oct 2022 13:36:30 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Thomas Zimmermann Subject: Re: [PATCH] drm/mgag200: Fix PLL setup for G200_SE_A rev >=4 Message-ID: References: <20221013082901.471417-1-jfalempe@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Patchwork-Hint: comment X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: airlied@redhat.com, Jocelyn Falempe , stable@vger.kernel.org, michel@daenzer.net, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, Oct 13, 2022 at 11:05:19AM +0200, Thomas Zimmermann wrote: > Hi > > Am 13.10.22 um 10:29 schrieb Jocelyn Falempe: > > For G200_SE_A, PLL M setting is wrong, which leads to blank screen, > > or "signal out of range" on VGA display. > > previous code had "m |= 0x80" which was changed to > > m |= ((pixpllcn & BIT(8)) >> 1); > > > > Tested on G200_SE_A rev 42 > > > > This line of code was moved to another file with > > commit 85397f6bc4ff ("drm/mgag200: Initialize each model in separate > > function") but can be easily backported before this commit. > > > > Fixes: 2dd040946ecf ("drm/mgag200: Store values (not bits) in struct mgag200_pll_values") > > Cc: stable@vger.kernel.org > > Signed-off-by: Jocelyn Falempe > > --- > > drivers/gpu/drm/mgag200/mgag200_g200se.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/mgag200/mgag200_g200se.c b/drivers/gpu/drm/mgag200/mgag200_g200se.c > > index be389ed91cbd..4ec035029b8b 100644 > > --- a/drivers/gpu/drm/mgag200/mgag200_g200se.c > > +++ b/drivers/gpu/drm/mgag200/mgag200_g200se.c > > @@ -284,7 +284,7 @@ static void mgag200_g200se_04_pixpllc_atomic_update(struct drm_crtc *crtc, > > pixpllcp = pixpllc->p - 1; > > pixpllcs = pixpllc->s; > > > > - xpixpllcm = pixpllcm | ((pixpllcn & BIT(8)) >> 1); > > + xpixpllcm = pixpllcm | BIT(7); > > Thanks for figuring this out. G200SE apparently is special compared to > the other models. The old MGA docs only list this bit as . > Really makes me wonder why this is different. Could measure eg. the vblank interval with and without that bit set and see what effect it has. Assuming the PLL locks without the bit of course. -- Ville Syrjälä Intel