All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>
Subject: Re: [PATCH v3 4/5] x86/mwait-idle: disable IBRS during long idle
Date: Fri, 14 Oct 2022 10:03:31 +0200	[thread overview]
Message-ID: <Y0ggOLWa7onsacmb@Air-de-Roger> (raw)
In-Reply-To: <dd2ca7b9-f7a3-208d-f757-cf47f37de1ab@suse.com>

On Thu, Oct 13, 2022 at 04:15:04PM +0200, Jan Beulich wrote:
> On 13.10.2022 15:10, Roger Pau Monné wrote:
> > On Thu, Oct 13, 2022 at 02:17:54PM +0200, Jan Beulich wrote:
> >> On 13.10.2022 14:03, Roger Pau Monné wrote:
> >>> On Thu, Aug 18, 2022 at 03:04:51PM +0200, Jan Beulich wrote:
> >>>> From: Peter Zijlstra <peterz@infradead.org>
> >>>>
> >>>> Having IBRS enabled while the SMT sibling is idle unnecessarily slows
> >>>> down the running sibling. OTOH, disabling IBRS around idle takes two
> >>>> MSR writes, which will increase the idle latency.
> >>>>
> >>>> Therefore, only disable IBRS around deeper idle states. Shallow idle
> >>>> states are bounded by the tick in duration, since NOHZ is not allowed
> >>>> for them by virtue of their short target residency.
> >>>>
> >>>> Only do this for mwait-driven idle, since that keeps interrupts disabled
> >>>> across idle, which makes disabling IBRS vs IRQ-entry a non-issue.
> >>>>
> >>>> Note: C6 is a random threshold, most importantly C1 probably shouldn't
> >>>> disable IBRS, benchmarking needed.
> >>>>
> >>>> Suggested-by: Tim Chen <tim.c.chen@linux.intel.com>
> >>>> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> >>>> Signed-off-by: Borislav Petkov <bp@suse.de>
> >>>> Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org>
> >>>> Signed-off-by: Borislav Petkov <bp@suse.de>
> >>>> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git bf5835bcdb96
> >>>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> >>>
> >>> Acked-by: Roger Pau Monné <roger.pau@citrix.com>
> >>
> >> Thanks.
> >>
> >>> One unrelated comment below.
> >>> [...]
> >>>> @@ -932,8 +939,6 @@ static void cf_check mwait_idle(void)
> >>>>  			pm_idle_save();
> >>>>  		else
> >>>>  		{
> >>>> -			struct cpu_info *info = get_cpu_info();
> >>>> -
> >>>>  			spec_ctrl_enter_idle(info);
> >>>>  			safe_halt();
> >>>>  			spec_ctrl_exit_idle(info);
> >>>
> >>> Do we need to disable speculation just for the hlt if there's no
> >>> C state change?
> >>>
> >>> It would seem to me like the MSR writes could add a lot of latency
> >>> when there's no C state change.
> >>
> >> HLT enters (at least) C1, so is a C-state change to me as well. Plus
> >> we may remain there for a while, and during that time we'd like to
> >> not unduly impact the other thread.
> > 
> > OK, but it's not a "deeper C state" as mentioned in the commit
> > message.
> 
> Correct. But it's also code not being altered by this commit.

Indeed, that's why it's an unrelated comment.  I was just wondering
whether we should drop those or not in a separate patch.  I'm
concerned over hitting that path on a virtualized environment, where
changing the spec controls is likely not that cheap.

Thanks, Roger.


  reply	other threads:[~2022-10-14  8:04 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-18 13:02 [PATCH v3 0/5] x86/mwait-idle: (remaining) SPR + (new) ADL support Jan Beulich
2022-08-18 13:03 ` [PATCH v3 1/5] x86/mwait-idle: add 'preferred-cstates' command line option Jan Beulich
2022-10-11 16:22   ` Roger Pau Monné
2022-10-12 13:46     ` Jan Beulich
2022-10-13 11:52   ` Roger Pau Monné
2022-08-18 13:03 ` [PATCH v3 2/5] x86/mwait-idle: add core C6 optimization for SPR Jan Beulich
2022-08-18 13:04 ` [PATCH v3 3/5] x86/mwait-idle: add AlderLake support Jan Beulich
2022-10-13 11:55   ` Roger Pau Monné
2022-08-18 13:04 ` [PATCH v3 4/5] x86/mwait-idle: disable IBRS during long idle Jan Beulich
2022-10-13 12:03   ` Roger Pau Monné
2022-10-13 12:17     ` Jan Beulich
2022-10-13 13:10       ` Roger Pau Monné
2022-10-13 14:15         ` Jan Beulich
2022-10-14  8:03           ` Roger Pau Monné [this message]
2022-10-14  8:53             ` Jan Beulich
2022-08-18 13:05 ` [PATCH v3 5/5] x86/mwait-idle: make SPR C1 and C1E be independent Jan Beulich
2022-10-13 12:05   ` Roger Pau Monné
2022-10-13 12:20     ` Jan Beulich
2022-08-18 13:09 ` [PATCH v3 0/5] x86/mwait-idle: (remaining) SPR + (new) ADL support Jan Beulich
2022-08-19  1:02   ` Henry Wang
2022-10-13 12:25 ` [4.17?] " Jan Beulich
2022-10-13 12:46   ` Henry Wang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=Y0ggOLWa7onsacmb@Air-de-Roger \
    --to=roger.pau@citrix.com \
    --cc=andrew.cooper3@citrix.com \
    --cc=jbeulich@suse.com \
    --cc=wl@xen.org \
    --cc=xen-devel@lists.xenproject.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.