From: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
To: Jacob Keller <jacob.e.keller@intel.com>
Cc: Jakub Kicinski <kuba@kernel.org>,
David Miller <davem@davemloft.net>, <netdev@vger.kernel.org>,
Lukasz Czapnik <lukasz.czapnik@intel.com>,
"Mateusz Palczewski" <mateusz.palczewski@intel.com>,
Gurucharan <gurucharanx.g@intel.com>
Subject: Re: [PATCH net-next] ice: Add additional CSR registers
Date: Wed, 26 Oct 2022 16:54:43 +0200 [thread overview]
Message-ID: <Y1lKM8RyqnPUbEv4@boxer> (raw)
In-Reply-To: <20221026112839.3623579-1-jacob.e.keller@intel.com>
On Wed, Oct 26, 2022 at 04:28:39AM -0700, Jacob Keller wrote:
> From: Lukasz Czapnik <lukasz.czapnik@intel.com>
>
> Add additional CSR registers that will provide more information
> in the dump that occurs after Tx hang.
So...where is the corresponding commit that would actually utilize some of
these additional regs? :p
>
> Signed-off-by: Lukasz Czapnik <lukasz.czapnik@intel.com>
> Signed-off-by: Mateusz Palczewski <mateusz.palczewski@intel.com>
> Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
> ---
> drivers/net/ethernet/intel/ice/ice_ethtool.c | 169 +++++++++++++++++++
> 1 file changed, 169 insertions(+)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c
> index b7be84bbe72d..f71a7521c7bd 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ethtool.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c
> @@ -151,6 +151,175 @@ static const u32 ice_regs_dump_list[] = {
> QINT_RQCTL(0),
> PFINT_OICR_ENA,
> QRX_ITR(0),
> +#define GLDCB_TLPM_PCI_DM 0x000A0180
> + GLDCB_TLPM_PCI_DM,
> +#define GLDCB_TLPM_TC2PFC 0x000A0194
> + GLDCB_TLPM_TC2PFC,
> +#define TCDCB_TLPM_WAIT_DM(_i) (0x000A0080 + ((_i) * 4))
> + TCDCB_TLPM_WAIT_DM(0),
> + TCDCB_TLPM_WAIT_DM(1),
> + TCDCB_TLPM_WAIT_DM(2),
> + TCDCB_TLPM_WAIT_DM(3),
> + TCDCB_TLPM_WAIT_DM(4),
> + TCDCB_TLPM_WAIT_DM(5),
> + TCDCB_TLPM_WAIT_DM(6),
> + TCDCB_TLPM_WAIT_DM(7),
> + TCDCB_TLPM_WAIT_DM(8),
> + TCDCB_TLPM_WAIT_DM(9),
> + TCDCB_TLPM_WAIT_DM(10),
> + TCDCB_TLPM_WAIT_DM(11),
> + TCDCB_TLPM_WAIT_DM(12),
> + TCDCB_TLPM_WAIT_DM(13),
> + TCDCB_TLPM_WAIT_DM(14),
> + TCDCB_TLPM_WAIT_DM(15),
> + TCDCB_TLPM_WAIT_DM(16),
> + TCDCB_TLPM_WAIT_DM(17),
> + TCDCB_TLPM_WAIT_DM(18),
> + TCDCB_TLPM_WAIT_DM(19),
> + TCDCB_TLPM_WAIT_DM(20),
> + TCDCB_TLPM_WAIT_DM(21),
> + TCDCB_TLPM_WAIT_DM(22),
> + TCDCB_TLPM_WAIT_DM(23),
> + TCDCB_TLPM_WAIT_DM(24),
> + TCDCB_TLPM_WAIT_DM(25),
> + TCDCB_TLPM_WAIT_DM(26),
> + TCDCB_TLPM_WAIT_DM(27),
> + TCDCB_TLPM_WAIT_DM(28),
> + TCDCB_TLPM_WAIT_DM(29),
> + TCDCB_TLPM_WAIT_DM(30),
> + TCDCB_TLPM_WAIT_DM(31),
> +#define GLPCI_WATMK_CLNT_PIPEMON 0x000BFD90
> + GLPCI_WATMK_CLNT_PIPEMON,
> +#define GLPCI_CUR_CLNT_COMMON 0x000BFD84
> + GLPCI_CUR_CLNT_COMMON,
> +#define GLPCI_CUR_CLNT_PIPEMON 0x000BFD88
> + GLPCI_CUR_CLNT_PIPEMON,
> +#define GLPCI_PCIERR 0x0009DEB0
> + GLPCI_PCIERR,
> +#define GLPSM_DEBUG_CTL_STATUS 0x000B0600
> + GLPSM_DEBUG_CTL_STATUS,
> +#define GLPSM0_DEBUG_FIFO_OVERFLOW_DETECT 0x000B0680
> + GLPSM0_DEBUG_FIFO_OVERFLOW_DETECT,
> +#define GLPSM0_DEBUG_FIFO_UNDERFLOW_DETECT 0x000B0684
> + GLPSM0_DEBUG_FIFO_UNDERFLOW_DETECT,
> +#define GLPSM0_DEBUG_DT_OUT_OF_WINDOW 0x000B0688
> + GLPSM0_DEBUG_DT_OUT_OF_WINDOW,
> +#define GLPSM0_DEBUG_INTF_HW_ERROR_DETECT 0x000B069C
> + GLPSM0_DEBUG_INTF_HW_ERROR_DETECT,
> +#define GLPSM0_DEBUG_MISC_HW_ERROR_DETECT 0x000B06A0
> + GLPSM0_DEBUG_MISC_HW_ERROR_DETECT,
> +#define GLPSM1_DEBUG_FIFO_OVERFLOW_DETECT 0x000B0E80
> + GLPSM1_DEBUG_FIFO_OVERFLOW_DETECT,
> +#define GLPSM1_DEBUG_FIFO_UNDERFLOW_DETECT 0x000B0E84
> + GLPSM1_DEBUG_FIFO_UNDERFLOW_DETECT,
> +#define GLPSM1_DEBUG_SRL_FIFO_OVERFLOW_DETECT 0x000B0E88
> + GLPSM1_DEBUG_SRL_FIFO_OVERFLOW_DETECT,
> +#define GLPSM1_DEBUG_SRL_FIFO_UNDERFLOW_DETECT 0x000B0E8C
> + GLPSM1_DEBUG_SRL_FIFO_UNDERFLOW_DETECT,
> +#define GLPSM1_DEBUG_MISC_HW_ERROR_DETECT 0x000B0E90
> + GLPSM1_DEBUG_MISC_HW_ERROR_DETECT,
> +#define GLPSM2_DEBUG_FIFO_OVERFLOW_DETECT 0x000B1680
> + GLPSM2_DEBUG_FIFO_OVERFLOW_DETECT,
> +#define GLPSM2_DEBUG_FIFO_UNDERFLOW_DETECT 0x000B1684
> + GLPSM2_DEBUG_FIFO_UNDERFLOW_DETECT,
> +#define GLPSM2_DEBUG_MISC_HW_ERROR_DETECT 0x000B1688
> + GLPSM2_DEBUG_MISC_HW_ERROR_DETECT,
> +#define GLTDPU_TCLAN_COMP_BOB(_i) (0x00049ADC + ((_i) * 4))
> + GLTDPU_TCLAN_COMP_BOB(1),
> + GLTDPU_TCLAN_COMP_BOB(2),
> + GLTDPU_TCLAN_COMP_BOB(3),
> + GLTDPU_TCLAN_COMP_BOB(4),
> + GLTDPU_TCLAN_COMP_BOB(5),
> + GLTDPU_TCLAN_COMP_BOB(6),
> + GLTDPU_TCLAN_COMP_BOB(7),
> + GLTDPU_TCLAN_COMP_BOB(8),
> +#define GLTDPU_TCB_CMD_BOB(_i) (0x0004975C + ((_i) * 4))
> + GLTDPU_TCB_CMD_BOB(1),
> + GLTDPU_TCB_CMD_BOB(2),
> + GLTDPU_TCB_CMD_BOB(3),
> + GLTDPU_TCB_CMD_BOB(4),
> + GLTDPU_TCB_CMD_BOB(5),
> + GLTDPU_TCB_CMD_BOB(6),
> + GLTDPU_TCB_CMD_BOB(7),
> + GLTDPU_TCB_CMD_BOB(8),
> +#define GLTDPU_PSM_UPDATE_BOB(_i) (0x00049B5C + ((_i) * 4))
> + GLTDPU_PSM_UPDATE_BOB(1),
> + GLTDPU_PSM_UPDATE_BOB(2),
> + GLTDPU_PSM_UPDATE_BOB(3),
> + GLTDPU_PSM_UPDATE_BOB(4),
> + GLTDPU_PSM_UPDATE_BOB(5),
> + GLTDPU_PSM_UPDATE_BOB(6),
> + GLTDPU_PSM_UPDATE_BOB(7),
> + GLTDPU_PSM_UPDATE_BOB(8),
> +#define GLTCB_CMD_IN_BOB(_i) (0x000AE288 + ((_i) * 4))
> + GLTCB_CMD_IN_BOB(1),
> + GLTCB_CMD_IN_BOB(2),
> + GLTCB_CMD_IN_BOB(3),
> + GLTCB_CMD_IN_BOB(4),
> + GLTCB_CMD_IN_BOB(5),
> + GLTCB_CMD_IN_BOB(6),
> + GLTCB_CMD_IN_BOB(7),
> + GLTCB_CMD_IN_BOB(8),
> +#define GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(_i) (0x000FC148 + ((_i) * 4))
> + GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(1),
> + GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(2),
> + GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(3),
> + GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(4),
> + GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(5),
> + GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(6),
> + GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(7),
> + GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(8),
> +#define GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(_i) (0x000FC248 + ((_i) * 4))
> + GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(1),
> + GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(2),
> + GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(3),
> + GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(4),
> + GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(5),
> + GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(6),
> + GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(7),
> + GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(8),
> +#define GLLAN_TCLAN_CACHE_CTL_BOB_CTL(_i) (0x000FC1C8 + ((_i) * 4))
> + GLLAN_TCLAN_CACHE_CTL_BOB_CTL(1),
> + GLLAN_TCLAN_CACHE_CTL_BOB_CTL(2),
> + GLLAN_TCLAN_CACHE_CTL_BOB_CTL(3),
> + GLLAN_TCLAN_CACHE_CTL_BOB_CTL(4),
> + GLLAN_TCLAN_CACHE_CTL_BOB_CTL(5),
> + GLLAN_TCLAN_CACHE_CTL_BOB_CTL(6),
> + GLLAN_TCLAN_CACHE_CTL_BOB_CTL(7),
> + GLLAN_TCLAN_CACHE_CTL_BOB_CTL(8),
> +#define GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(_i) (0x000FC188 + ((_i) * 4))
> + GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(1),
> + GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(2),
> + GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(3),
> + GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(4),
> + GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(5),
> + GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(6),
> + GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(7),
> + GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(8),
> +#define GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(_i) (0x000FC288 + ((_i) * 4))
> + GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(1),
> + GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(2),
> + GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(3),
> + GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(4),
> + GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(5),
> + GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(6),
> + GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(7),
> + GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(8),
> +#define PRTDCB_TCUPM_REG_CM(_i) (0x000BC360 + ((_i) * 4))
> + PRTDCB_TCUPM_REG_CM(0),
> + PRTDCB_TCUPM_REG_CM(1),
> + PRTDCB_TCUPM_REG_CM(2),
> + PRTDCB_TCUPM_REG_CM(3),
> +#define PRTDCB_TCUPM_REG_DM(_i) (0x000BC3A0 + ((_i) * 4))
> + PRTDCB_TCUPM_REG_DM(0),
> + PRTDCB_TCUPM_REG_DM(1),
> + PRTDCB_TCUPM_REG_DM(2),
> + PRTDCB_TCUPM_REG_DM(3),
> +#define PRTDCB_TLPM_REG_DM(_i) (0x000A0000 + ((_i) * 4))
> + PRTDCB_TLPM_REG_DM(0),
> + PRTDCB_TLPM_REG_DM(1),
> + PRTDCB_TLPM_REG_DM(2),
> + PRTDCB_TLPM_REG_DM(3),
> };
>
> struct ice_priv_flag {
>
> base-commit: d0217284cea7d470e4140e98b806cb3cdf8257d6
> --
> 2.38.0.83.gd420dda05763
>
next prev parent reply other threads:[~2022-10-26 14:55 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-26 11:28 [PATCH net-next] ice: Add additional CSR registers Jacob Keller
2022-10-26 14:54 ` Maciej Fijalkowski [this message]
2022-10-27 9:20 ` Keller, Jacob E
2022-10-27 10:15 ` Maciej Fijalkowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Y1lKM8RyqnPUbEv4@boxer \
--to=maciej.fijalkowski@intel.com \
--cc=davem@davemloft.net \
--cc=gurucharanx.g@intel.com \
--cc=jacob.e.keller@intel.com \
--cc=kuba@kernel.org \
--cc=lukasz.czapnik@intel.com \
--cc=mateusz.palczewski@intel.com \
--cc=netdev@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.