From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26660C433FE for ; Wed, 26 Oct 2022 17:32:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233745AbiJZRcl (ORCPT ); Wed, 26 Oct 2022 13:32:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233585AbiJZRck (ORCPT ); Wed, 26 Oct 2022 13:32:40 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7CA6103DBD for ; Wed, 26 Oct 2022 10:32:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666805559; x=1698341559; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=/if8DQ5EflrQr8sz6S1J4sRbItNVfPHM8ngYZIIISek=; b=Yqjb8FCDshnpxWvf9sCgMjuWDpbUyOgG4ZsTK/2dN+8WawVNsteHaIvC dKM3b5fHbC6irhMY/clr1r2Db242/0soqrGRhrJBksbvHD3yf+XVT3EJe v0KY6q0oOEy7HGwxofM3dxBYu0EmUDNk8//+oqan9rTMCFDcLIWG7RaFp cA0NyIJ38iSxPyAYM170EEJagy19doblhkS7UZ2+fYrhy7kkaYpfcwlNW 0ixDHJ0Vwc5EYKrvZWnNu5cREv1eUE+DBkKh1zCfI5xi2QdlAg0dr5866 82oNSkzsU+pJ9GvT/MvkzeWdDHiCoG59LdwbIK+YpkKBzFjumoHymbRDm g==; X-IronPort-AV: E=McAfee;i="6500,9779,10512"; a="308008194" X-IronPort-AV: E=Sophos;i="5.95,215,1661842800"; d="scan'208";a="308008194" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2022 10:32:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10512"; a="877274486" X-IronPort-AV: E=Sophos;i="5.95,215,1661842800"; d="scan'208";a="877274486" Received: from smile.fi.intel.com ([10.237.72.54]) by fmsmga006.fm.intel.com with ESMTP; 26 Oct 2022 10:32:37 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.96) (envelope-from ) id 1onkGY-002lzP-2y; Wed, 26 Oct 2022 20:32:34 +0300 Date: Wed, 26 Oct 2022 20:32:34 +0300 From: Andy Shevchenko To: Levente =?iso-8859-1?B?Uul26XN6?= Cc: Linus Walleij , Bartosz Golaszewski , Martyn Welch , Haibo Chen , Puyou Lu , Justin Chen , Andrey Gusakov , Nate Drude , linux-gpio@vger.kernel.org Subject: Re: [PATCH v2 5/6] gpio: pca953x: Add interrupt mask support for chips with the standard register set Message-ID: References: <9df1a016-36be-14b7-9674-d18c7df208c7@eilabs.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <9df1a016-36be-14b7-9674-d18c7df208c7@eilabs.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Wed, Oct 26, 2022 at 01:25:23PM +0200, Levente Révész wrote: > Some chips in the pca953x family in addition to the standard 4 > registers have a fifth interrupt mask register: > > 0: INPUT > 1: OUTPUT > 2: POLARITY > 3: CONFIGURATION > 4: INTERRUPT MASK > > Chips with this register: > > - pca9505 > - pca9506 > - pca9698 > > This register defaults to all interrupts disabled. The driver has to set > the register to use interrupts with these chips. > > Add PCA953X_INT_MASK register. Use it as the interrupt register of > (non-pcal) pca953x chips. > > Set pca9505 and pca9506 to use this register. Please, compile each patch in the series separately (incremental building). -- With Best Regards, Andy Shevchenko