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From: Leo Liang <ycliang@andestech.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Rick Chen <rick@andestech.com>, Lukasz Majewski <lukma@denx.de>,
	"Sean Anderson" <seanga2@gmail.com>,
	Padmarao Begari <padmarao.begari@microchip.com>,
	<u-boot@lists.denx.de>
Subject: Re: [PATCH v1 2/6] clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()
Date: Wed, 2 Nov 2022 11:20:26 +0000	[thread overview]
Message-ID: <Y2JSegpNEKXG1dQC@ubuntu01> (raw)
In-Reply-To: <20221025075848.110754-3-conor.dooley@microchip.com>

On Tue, Oct 25, 2022 at 08:58:45AM +0100, Conor Dooley wrote:
> Currently the clock driver for PolarFire SoC takes a very naive approach
> to the relationship between clocks. It reads the dt to get an input
> clock, assumes that that is fixed frequency, reads the "clock-frequency"
> property & uses that to set up both the "cfg" and "periph" clocks.
> 
> Simplifying for the sake of incremental fixes, the "correct" parentage for
> the clocks currently supported in U-Boot is that the "cfg" clocks should
> be children of the fixed frequency clock in the dt. The AHB clock is one
> of these "cfg" clocks and is the parent of the "periph" clocks.
> 
> Instead of passing the clock rate of the fixed-frequency clock to the
> "cfg" and "periph" registration functions and the name of the parents,
> pass their actual parents & use clk_get_rate() to determine their parents
> rates.
> 
> The "periph" clocks are purely gate clocks and should not be reading the
> AHB clocks registers to determine their rates, as they can simply report
> the output of clk_get_rate() on their parent.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  drivers/clk/microchip/Makefile          |  2 +-
>  drivers/clk/microchip/mpfs_clk.c        | 18 ++++++++----------
>  drivers/clk/microchip/mpfs_clk.h        | 12 ++++--------
>  drivers/clk/microchip/mpfs_clk_cfg.c    |  7 +++----
>  drivers/clk/microchip/mpfs_clk_periph.c | 16 ++++------------
>  5 files changed, 20 insertions(+), 35 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

  reply	other threads:[~2022-11-02 11:20 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-25  7:58 [PATCH v1 0/6] clk: microchip: mpfs: incremental fixes Conor Dooley
2022-10-25  7:58 ` [PATCH v1 1/6] dt-bindings: clk: add missing clk ids for microchip mpfs Conor Dooley
2022-11-02 11:19   ` Leo Liang
2022-11-02 13:20   ` Padmarao.Begari
2022-10-25  7:58 ` [PATCH v1 2/6] clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() Conor Dooley
2022-11-02 11:20   ` Leo Liang [this message]
2022-11-02 13:20   ` Padmarao.Begari
2022-11-02 16:41     ` Conor Dooley
2022-10-25  7:58 ` [PATCH v1 3/6] clk: microchip: mpfs: fix reference clock handling Conor Dooley
2022-11-02 11:21   ` Leo Liang
2022-11-02 13:20   ` Padmarao.Begari
2022-10-25  7:58 ` [PATCH v1 4/6] clk: microchip: mpfs: fix periph clk parentage Conor Dooley
2022-11-02 11:21   ` Leo Liang
2022-11-02 13:20   ` Padmarao.Begari
2022-10-25  7:58 ` [PATCH v1 5/6] clk: microchip: mpfs: fix criticality of peripheral clocks Conor Dooley
2022-11-02 11:22   ` Leo Liang
2022-11-02 13:20   ` Padmarao.Begari
2022-10-25  7:58 ` [PATCH v1 6/6] riscv: dts: fix the mpfs's reference clock frequency Conor Dooley
2022-11-02 11:22   ` Leo Liang
2022-11-02 13:21   ` Padmarao.Begari

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