From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Christopherson Date: Thu, 3 Nov 2022 18:35:05 +0000 Subject: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code In-Reply-To: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> Message-ID: List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 00:19, Sean Christopherson wrote: > > + if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || > > + !boot_cpu_has(X86_FEATURE_VMX)) { > > + pr_err("VMX not enabled in MSR_IA32_FEAT_CTL\n"); > > + return false; > > I think the reference to the BIOS should remain in these messages and in > svm.c (even though these days it's much less common for vendors to default > to disabled virtualization in the system setup). Ya, I'll figure out a way to mention BIOS/firmware. > The check for X86_FEATURE_MSR_IA32_FEAT_CTL is not needed because > init_ia32_feat_ctl() will clear X86_FEATURE_VMX if the rdmsr fail (and not > set X86_FEATURE_MSR_IA32_FEAT_CTL). It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only if the actual CPU type matches one of the aforementioned CPU_SUP_*. E.g. running a kernel built with CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y # CONFIG_CPU_SUP_HYGON is not set # CONFIG_CPU_SUP_CENTAUR is not set # CONFIG_CPU_SUP_ZHAOXIN is not set on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM will get unexpected #UDs when trying to enable VMX. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80F70C43219 for ; Thu, 3 Nov 2022 18:35:14 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id DB1474B355; Thu, 3 Nov 2022 14:35:13 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@google.com Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wZMhzwmL+lDo; Thu, 3 Nov 2022 14:35:12 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id C42AE4B1B7; Thu, 3 Nov 2022 14:35:12 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 4A4144B199 for ; Thu, 3 Nov 2022 14:35:11 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 83sOFlCb0aIV for ; Thu, 3 Nov 2022 14:35:10 -0400 (EDT) Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 35C6D410F3 for ; Thu, 3 Nov 2022 14:35:10 -0400 (EDT) Received: by mail-pl1-f177.google.com with SMTP id y4so2762845plb.2 for ; Thu, 03 Nov 2022 11:35:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=dgoOqWPJe20h3F3t+kWJTAR37+M7sNOsPG89iz5Bulk=; b=Pm4Lr3kAm7G9yhV3E+texinWexF8/BykknHnX+41QMhdAJg8Q6KGdsZlwDR9KsaQ03 q0oiA6QGnfMNaCLi6FwippomEY2Gxx8DIbtsls7Wm3K9Y5ntAz6T/fo5rOOGqR0XZexV IMpIarVZKtd2r4wbd6pBH2HWWgUKLdmEcjKjz7hr2eZWqilU2ZOjSL0LQYBIbuLk+an3 F080UdTs/Pl//2c4Y7M3MC5aXIj0L8ze9uKQnOS3RTfUxOdNjPBYkRT7wM2xznbkkPNf k6rWzEiCMkA6YZikO6kTaZUjEx2R8QJERpkjNDf1cNtL0uRiWX1pfQEgD4PMO8IN1GPi cqnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=dgoOqWPJe20h3F3t+kWJTAR37+M7sNOsPG89iz5Bulk=; b=muBV+1kfj21/1gc1GI7En3ZS/tNVVjzwZSzoXJvGWU0yEOwBac3BVAqzUao3nHpV7X l5Fte7UV+Xs4zzRmu6/5y4xRh8P5bGjTR9U+1owrfZ4G0MIIGfiJmaX34FKbSqw0ECdT 3pHcQdo2gSNKNDmv/hd7vJh/ujjtL3jEROXkFLqHfnuitO3XqBqg2r9UYwoaaPT+Ybhv cspmChmPZMvTZ6X9oiiqVG/a56YOZ+Ge/rIVvzS5yBrAHW5PMZR+BblK9f1Np4pPPev+ FiGXPD4g9XuoBn5oSiAYJS/auXu+DSIXvTMeCEsM62oLQGF67/8azgJdJ8XKLEEFI4/L 8Isw== X-Gm-Message-State: ACrzQf1ufJA9QPpBFrHkYM7fcSwHexUJsHXgbzka/cMnEaO7cg3jtduh H/M53Ci3ZSgxKVbmO9c4l+RReg== X-Google-Smtp-Source: AMsMyM7An2PKDpytAFzn8oRI/SQJomdGS1nTfx9CsrnDxhHyyoY4AD/5FsaR2YoYMTMl2oHfbxu0kQ== X-Received: by 2002:a17:903:1250:b0:185:40c6:3c2c with SMTP id u16-20020a170903125000b0018540c63c2cmr31387342plh.64.1667500509087; Thu, 03 Nov 2022 11:35:09 -0700 (PDT) Received: from google.com (7.104.168.34.bc.googleusercontent.com. [34.168.104.7]) by smtp.gmail.com with ESMTPSA id z4-20020a1709027e8400b0017da2798025sm914686pla.295.2022.11.03.11.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 11:35:08 -0700 (PDT) Date: Thu, 3 Nov 2022 18:35:05 +0000 From: Sean Christopherson To: Paolo Bonzini Subject: Re: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code Message-ID: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: Matthew Rosato , David Hildenbrand , Yuan Yao , Paul Walmsley , linux-kernel@vger.kernel.org, Michael Ellerman , linux-riscv@lists.infradead.org, Claudio Imbrenda , kvmarm@lists.cs.columbia.edu, linux-s390@vger.kernel.org, Janosch Frank , Marc Zyngier , Huacai Chen , Aleksandar Markovic , Christian Borntraeger , Chao Gao , Eric Farman , Albert Ou , kvm@vger.kernel.org, Atish Patra , kvmarm@lists.linux.dev, Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Isaku Yamahata , Fabiano Rosas , linux-mips@vger.kernel.org, Palmer Dabbelt , kvm-riscv@lists.infradead.org, Vitaly Kuznetsov , linuxppc-dev@lists.ozlabs.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 00:19, Sean Christopherson wrote: > > + if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || > > + !boot_cpu_has(X86_FEATURE_VMX)) { > > + pr_err("VMX not enabled in MSR_IA32_FEAT_CTL\n"); > > + return false; > > I think the reference to the BIOS should remain in these messages and in > svm.c (even though these days it's much less common for vendors to default > to disabled virtualization in the system setup). Ya, I'll figure out a way to mention BIOS/firmware. > The check for X86_FEATURE_MSR_IA32_FEAT_CTL is not needed because > init_ia32_feat_ctl() will clear X86_FEATURE_VMX if the rdmsr fail (and not > set X86_FEATURE_MSR_IA32_FEAT_CTL). It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only if the actual CPU type matches one of the aforementioned CPU_SUP_*. E.g. running a kernel built with CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y # CONFIG_CPU_SUP_HYGON is not set # CONFIG_CPU_SUP_CENTAUR is not set # CONFIG_CPU_SUP_ZHAOXIN is not set on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM will get unexpected #UDs when trying to enable VMX. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C50AC29A8 for ; Thu, 3 Nov 2022 18:35:09 +0000 (UTC) Received: by mail-pj1-f45.google.com with SMTP id d59-20020a17090a6f4100b00213202d77e1so6087994pjk.2 for ; Thu, 03 Nov 2022 11:35:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=dgoOqWPJe20h3F3t+kWJTAR37+M7sNOsPG89iz5Bulk=; b=Pm4Lr3kAm7G9yhV3E+texinWexF8/BykknHnX+41QMhdAJg8Q6KGdsZlwDR9KsaQ03 q0oiA6QGnfMNaCLi6FwippomEY2Gxx8DIbtsls7Wm3K9Y5ntAz6T/fo5rOOGqR0XZexV IMpIarVZKtd2r4wbd6pBH2HWWgUKLdmEcjKjz7hr2eZWqilU2ZOjSL0LQYBIbuLk+an3 F080UdTs/Pl//2c4Y7M3MC5aXIj0L8ze9uKQnOS3RTfUxOdNjPBYkRT7wM2xznbkkPNf k6rWzEiCMkA6YZikO6kTaZUjEx2R8QJERpkjNDf1cNtL0uRiWX1pfQEgD4PMO8IN1GPi cqnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=dgoOqWPJe20h3F3t+kWJTAR37+M7sNOsPG89iz5Bulk=; b=68PJDqK6vxlDRj6mCQSuCJS0XKQDXmNzfTHzWWuRQzLtxqYfaWrGWSW3zZazMBWd5s rTMCjL1cF3xUN4ZDlMUGRhBP8h9RjD+Bz2Lh8S9q4WoI1BWBL0S3ZoSWhCGo+vKx+YDM iChvXwi+pQu5MiuFZwid6Xavt2aHBEUFKEn60hx9bKmnh6b1CvZqsq729/Rq6HhTQ+vj PzA5r2+J4XVc20MNQFUuyJK7s5NARosK3HRLbywrnRGwEEHUGfwE4HxY+LbA/1uboPvv koqSdqbzyXWPOivxDxdQ9LOTMtvPv1/6MjzBGXnPaT50HdkoAz3Ag6C/V6DO5PnOTDOv qoMw== X-Gm-Message-State: ACrzQf3nKmS1a+Sk8sJOMRa/cpMKBDcUHEI/XcxwUnzPmv9ol1OjEKCg FTE2XYQn0n6EiD0Q5pMhnEssQw== X-Google-Smtp-Source: AMsMyM7An2PKDpytAFzn8oRI/SQJomdGS1nTfx9CsrnDxhHyyoY4AD/5FsaR2YoYMTMl2oHfbxu0kQ== X-Received: by 2002:a17:903:1250:b0:185:40c6:3c2c with SMTP id u16-20020a170903125000b0018540c63c2cmr31387342plh.64.1667500509087; Thu, 03 Nov 2022 11:35:09 -0700 (PDT) Received: from google.com (7.104.168.34.bc.googleusercontent.com. [34.168.104.7]) by smtp.gmail.com with ESMTPSA id z4-20020a1709027e8400b0017da2798025sm914686pla.295.2022.11.03.11.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 11:35:08 -0700 (PDT) Date: Thu, 3 Nov 2022 18:35:05 +0000 From: Sean Christopherson To: Paolo Bonzini Cc: Marc Zyngier , Huacai Chen , Aleksandar Markovic , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Christian Borntraeger , Janosch Frank , Claudio Imbrenda , Matthew Rosato , Eric Farman , Vitaly Kuznetsov , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Atish Patra , David Hildenbrand , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-kernel@vger.kernel.org, Isaku Yamahata , Fabiano Rosas , Michael Ellerman , Chao Gao , Thomas Gleixner , Yuan Yao Subject: Re: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code Message-ID: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Message-ID: <20221103183505.GZI5Flkf3V9qgw6OgsKVi0b5bh9KTFBK_jENEftOztM@z> On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 00:19, Sean Christopherson wrote: > > + if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || > > + !boot_cpu_has(X86_FEATURE_VMX)) { > > + pr_err("VMX not enabled in MSR_IA32_FEAT_CTL\n"); > > + return false; > > I think the reference to the BIOS should remain in these messages and in > svm.c (even though these days it's much less common for vendors to default > to disabled virtualization in the system setup). Ya, I'll figure out a way to mention BIOS/firmware. > The check for X86_FEATURE_MSR_IA32_FEAT_CTL is not needed because > init_ia32_feat_ctl() will clear X86_FEATURE_VMX if the rdmsr fail (and not > set X86_FEATURE_MSR_IA32_FEAT_CTL). It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only if the actual CPU type matches one of the aforementioned CPU_SUP_*. E.g. running a kernel built with CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y # CONFIG_CPU_SUP_HYGON is not set # CONFIG_CPU_SUP_CENTAUR is not set # CONFIG_CPU_SUP_ZHAOXIN is not set on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM will get unexpected #UDs when trying to enable VMX. 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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id z4-20020a1709027e8400b0017da2798025sm914686pla.295.2022.11.03.11.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 11:35:08 -0700 (PDT) Date: Thu, 3 Nov 2022 18:35:05 +0000 From: Sean Christopherson To: Paolo Bonzini Cc: Marc Zyngier , Huacai Chen , Aleksandar Markovic , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Christian Borntraeger , Janosch Frank , Claudio Imbrenda , Matthew Rosato , Eric Farman , Vitaly Kuznetsov , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Atish Patra , David Hildenbrand , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-kernel@vger.kernel.org, Isaku Yamahata , Fabiano Rosas , Michael Ellerman , Chao Gao , Thomas Gleixner , Yuan Yao Subject: Re: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code Message-ID: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221103_113514_594533_13A2EF2D X-CRM114-Status: GOOD ( 14.65 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 00:19, Sean Christopherson wrote: > > + if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || > > + !boot_cpu_has(X86_FEATURE_VMX)) { > > + pr_err("VMX not enabled in MSR_IA32_FEAT_CTL\n"); > > + return false; > > I think the reference to the BIOS should remain in these messages and in > svm.c (even though these days it's much less common for vendors to default > to disabled virtualization in the system setup). Ya, I'll figure out a way to mention BIOS/firmware. > The check for X86_FEATURE_MSR_IA32_FEAT_CTL is not needed because > init_ia32_feat_ctl() will clear X86_FEATURE_VMX if the rdmsr fail (and not > set X86_FEATURE_MSR_IA32_FEAT_CTL). It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only if the actual CPU type matches one of the aforementioned CPU_SUP_*. E.g. running a kernel built with CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y # CONFIG_CPU_SUP_HYGON is not set # CONFIG_CPU_SUP_CENTAUR is not set # CONFIG_CPU_SUP_ZHAOXIN is not set on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM will get unexpected #UDs when trying to enable VMX. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66CE5C4332F for ; Thu, 3 Nov 2022 18:36:10 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4N3CBd01qRz3ccv for ; Fri, 4 Nov 2022 05:36:09 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20210112 header.b=Pm4Lr3kA; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=google.com (client-ip=2607:f8b0:4864:20::102a; helo=mail-pj1-x102a.google.com; envelope-from=seanjc@google.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20210112 header.b=Pm4Lr3kA; dkim-atps=neutral Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4N3C9Y1msHz3c5D for ; Fri, 4 Nov 2022 05:35:12 +1100 (AEDT) Received: by mail-pj1-x102a.google.com with SMTP id e7-20020a17090a77c700b00216928a3917so1231365pjs.4 for ; Thu, 03 Nov 2022 11:35:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=dgoOqWPJe20h3F3t+kWJTAR37+M7sNOsPG89iz5Bulk=; b=Pm4Lr3kAm7G9yhV3E+texinWexF8/BykknHnX+41QMhdAJg8Q6KGdsZlwDR9KsaQ03 q0oiA6QGnfMNaCLi6FwippomEY2Gxx8DIbtsls7Wm3K9Y5ntAz6T/fo5rOOGqR0XZexV IMpIarVZKtd2r4wbd6pBH2HWWgUKLdmEcjKjz7hr2eZWqilU2ZOjSL0LQYBIbuLk+an3 F080UdTs/Pl//2c4Y7M3MC5aXIj0L8ze9uKQnOS3RTfUxOdNjPBYkRT7wM2xznbkkPNf k6rWzEiCMkA6YZikO6kTaZUjEx2R8QJERpkjNDf1cNtL0uRiWX1pfQEgD4PMO8IN1GPi cqnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=dgoOqWPJe20h3F3t+kWJTAR37+M7sNOsPG89iz5Bulk=; b=jxdi5h/BH/n4uY5cu3OCHmyno2rjGbfiPvp2diEOJBHNWsoG+oTyYPjfYwgX97l89j tD/rQJA7PjhIpGrcRbXKpi73gNIrTacZQ4dszRvTwxd92yVaxTxk0JC0ddCV1IZUOLOA RWZ4WNi2HJh+39tABnbGTGv4IUy4o/K+tUmY/DPWPMshb3XGSCuDvUJ01/sV9IUVDPw2 zQ9lGoX3Fuv4rrKb9D7qq9UWv4F/c7+gqvO9x+J6xZzW5KyXslKoY+7CrTvIVwi/dUKL /aV+7k1lABwFKq2gGJnbnkhKEE2WKPkNTpHgbpsxLFERna4l01IhrnrkiLqKBTb86CJc o7MA== X-Gm-Message-State: ACrzQf1RKBlqKtEhlFJ5wtkrV6HG72frmMlyqatrC6IHwQnSeIs7GA3h IKFog1kPbBC617vCpsns0/dokw== X-Google-Smtp-Source: AMsMyM7An2PKDpytAFzn8oRI/SQJomdGS1nTfx9CsrnDxhHyyoY4AD/5FsaR2YoYMTMl2oHfbxu0kQ== X-Received: by 2002:a17:903:1250:b0:185:40c6:3c2c with SMTP id u16-20020a170903125000b0018540c63c2cmr31387342plh.64.1667500509087; Thu, 03 Nov 2022 11:35:09 -0700 (PDT) Received: from google.com (7.104.168.34.bc.googleusercontent.com. [34.168.104.7]) by smtp.gmail.com with ESMTPSA id z4-20020a1709027e8400b0017da2798025sm914686pla.295.2022.11.03.11.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 11:35:08 -0700 (PDT) Date: Thu, 3 Nov 2022 18:35:05 +0000 From: Sean Christopherson To: Paolo Bonzini Subject: Re: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code Message-ID: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Rosato , David Hildenbrand , Yuan Yao , Paul Walmsley , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Claudio Imbrenda , kvmarm@lists.cs.columbia.edu, linux-s390@vger.kernel.org, Janosch Frank , Marc Zyngier , Huacai Chen , Aleksandar Markovic , James Morse , Christian Borntraeger , Chao Gao , Eric Farman , Albert Ou , Suzuki K Poulose , kvm@vger.kernel.org, Atish Patra , kvmarm@lists.linux.dev, Thomas Gleixner , Alexandru Elisei , linux-arm-kernel@lists.infradead.org, Isaku Yamahata , Fabiano Rosas , linux-mips@vger.kernel.org, Oliver Upton , Palmer Dabbelt , kvm-riscv@lists.infradead.org, Anup Patel , Vitaly Kuznetsov , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 00:19, Sean Christopherson wrote: > > + if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || > > + !boot_cpu_has(X86_FEATURE_VMX)) { > > + pr_err("VMX not enabled in MSR_IA32_FEAT_CTL\n"); > > + return false; > > I think the reference to the BIOS should remain in these messages and in > svm.c (even though these days it's much less common for vendors to default > to disabled virtualization in the system setup). Ya, I'll figure out a way to mention BIOS/firmware. > The check for X86_FEATURE_MSR_IA32_FEAT_CTL is not needed because > init_ia32_feat_ctl() will clear X86_FEATURE_VMX if the rdmsr fail (and not > set X86_FEATURE_MSR_IA32_FEAT_CTL). It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only if the actual CPU type matches one of the aforementioned CPU_SUP_*. E.g. running a kernel built with CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y # CONFIG_CPU_SUP_HYGON is not set # CONFIG_CPU_SUP_CENTAUR is not set # CONFIG_CPU_SUP_ZHAOXIN is not set on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM will get unexpected #UDs when trying to enable VMX. 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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id z4-20020a1709027e8400b0017da2798025sm914686pla.295.2022.11.03.11.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 11:35:08 -0700 (PDT) Date: Thu, 3 Nov 2022 18:35:05 +0000 From: Sean Christopherson To: Paolo Bonzini Cc: Marc Zyngier , Huacai Chen , Aleksandar Markovic , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Christian Borntraeger , Janosch Frank , Claudio Imbrenda , Matthew Rosato , Eric Farman , Vitaly Kuznetsov , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Atish Patra , David Hildenbrand , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-kernel@vger.kernel.org, Isaku Yamahata , Fabiano Rosas , Michael Ellerman , Chao Gao , Thomas Gleixner , Yuan Yao Subject: Re: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code Message-ID: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221103_113513_717523_40F997E5 X-CRM114-Status: GOOD ( 16.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 00:19, Sean Christopherson wrote: > > + if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || > > + !boot_cpu_has(X86_FEATURE_VMX)) { > > + pr_err("VMX not enabled in MSR_IA32_FEAT_CTL\n"); > > + return false; > > I think the reference to the BIOS should remain in these messages and in > svm.c (even though these days it's much less common for vendors to default > to disabled virtualization in the system setup). Ya, I'll figure out a way to mention BIOS/firmware. > The check for X86_FEATURE_MSR_IA32_FEAT_CTL is not needed because > init_ia32_feat_ctl() will clear X86_FEATURE_VMX if the rdmsr fail (and not > set X86_FEATURE_MSR_IA32_FEAT_CTL). It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only if the actual CPU type matches one of the aforementioned CPU_SUP_*. E.g. running a kernel built with CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y # CONFIG_CPU_SUP_HYGON is not set # CONFIG_CPU_SUP_CENTAUR is not set # CONFIG_CPU_SUP_ZHAOXIN is not set on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM will get unexpected #UDs when trying to enable VMX. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel