From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Christopherson Date: Thu, 3 Nov 2022 18:58:16 +0000 Subject: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code In-Reply-To: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> Message-ID: List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 19:35, Sean Christopherson wrote: > > It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of > > CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only > > if the actual CPU type matches one of the aforementioned CPU_SUP_*. > > > > E.g. running a kernel built with > > > > CONFIG_CPU_SUP_INTEL=y > > CONFIG_CPU_SUP_AMD=y > > # CONFIG_CPU_SUP_HYGON is not set > > # CONFIG_CPU_SUP_CENTAUR is not set > > # CONFIG_CPU_SUP_ZHAOXIN is not set > > > > on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set > > X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM > > will get unexpected #UDs when trying to enable VMX. > > Oh, I see. Perhaps X86_FEATURE_VMX and X86_FEATURE_SGX should be moved to > one of the software words instead of using cpuid. Nothing that you should > care about for this series though. Or maybe something like this? diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..ebe617ab0b37 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -191,6 +191,8 @@ static void default_init(struct cpuinfo_x86 *c) strcpy(c->x86_model_id, "386"); } #endif + + clear_cpu_cap(c, X86_FEATURE_MSR_IA32_FEAT_CTL); } static const struct cpu_dev default_cpu = { diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index c881bcafba7d..3a7ae67f5a5e 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -72,6 +72,8 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, { X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA }, + { X86_FEATURE_VMX, X86_FEATURE_MSR_IA32_FEAT_CTL }, + { X86_FEATURE_SGX, X86_FEATURE_MSR_IA32_FEAT_CTL }, { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3BB2C43219 for ; Thu, 3 Nov 2022 18:58:26 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 43FAB4B092; Thu, 3 Nov 2022 14:58:26 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@google.com Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id csSbojjwe75u; Thu, 3 Nov 2022 14:58:25 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 06E394B24D; Thu, 3 Nov 2022 14:58:25 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id F0C7349E1A for ; Thu, 3 Nov 2022 14:58:22 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TCtrYvd8qMHY for ; Thu, 3 Nov 2022 14:58:22 -0400 (EDT) Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id DB518412AC for ; Thu, 3 Nov 2022 14:58:21 -0400 (EDT) Received: by mail-pg1-f169.google.com with SMTP id b62so2504850pgc.0 for ; Thu, 03 Nov 2022 11:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=OgBlWniGTXEnPcASGuNFCxIZuwOSNaqHJ+Eb2HtkZ3A=; b=crtTNSDLBpNcvDSxofCENmrvtDvGgpUzGCkxI3/S4zR915QtnPiMfGmQ1bfa1+IphI JYKHG76keqoKUqskuvBrM1m0JyELxmvNXlZ4KiPUOKMYgaWfFysvap9RGXI963+2hoeq HHT/GX+S1XBR2PYehjOUxetwVpL78GGV9aYozWyKXyCWQQP6iGe8zgNPOME2bv1qjA9e apMslXORbm1rWkX1K/6OQ1RCG98VSwtHOf2J04nfLy9jITyFIIcn6ieZ9TY4AUm1gsGc eyQU7zbjJP0kGKm2zN/8wgEWv2C3dUA3cPXDwDYFGn1wLuJmRxozNVKQFEnfavfSL6Lx ZqXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=OgBlWniGTXEnPcASGuNFCxIZuwOSNaqHJ+Eb2HtkZ3A=; b=k0b3/PP5/oTxcSrT9UsGahedH/AuiFesR97eXgRNjAPr20x3nx1zF6+Yj/15fnyU+M xf8N5gIwBi9FeJLpCBR6guJGeBi5ed8yPyy9qJrnxKCdudHDpZgLnHmABRLrbE75Q6pe 4vsA06qj+V+bZ4m8GXEA1C/vjel/tgy0YlRHwiuJnvAzKuyDePYZD/FG+te+6+VlLS8n CzwcrmL5JsPIJ9W2s7lYf5NY90tVQaZYeS1BUBYyEFReP31mOF+VIvuml2dDbtzgC5UU uZuL2tIuQZeGXYTOy2UHmLUzrXzs23XZ5pdTVgzsM0ItfCEu/mZXr/dSeTV+jwKojuRR 754g== X-Gm-Message-State: ACrzQf3X+cZrGrCJkmO4kmEQIkFI48LXEthOKP5QgAC+ZEXwAXVHX7hE T1o9YlI8LnNO7IXIu83G/gqJeg== X-Google-Smtp-Source: AMsMyM7lUXjnrFRO+e+xTY8enXMXmh/YC+M/IqwbxJRPxqwsuhxb3fUJPK1b1MpOBO3HsUEvz+aKuA== X-Received: by 2002:aa7:81cf:0:b0:561:7d72:73ef with SMTP id c15-20020aa781cf000000b005617d7273efmr31655060pfn.16.1667501900762; Thu, 03 Nov 2022 11:58:20 -0700 (PDT) Received: from google.com (7.104.168.34.bc.googleusercontent.com. [34.168.104.7]) by smtp.gmail.com with ESMTPSA id c20-20020a17090ad91400b00209a12b3879sm309308pjv.37.2022.11.03.11.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 11:58:20 -0700 (PDT) Date: Thu, 3 Nov 2022 18:58:16 +0000 From: Sean Christopherson To: Paolo Bonzini Subject: Re: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code Message-ID: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: Matthew Rosato , David Hildenbrand , Yuan Yao , Paul Walmsley , linux-kernel@vger.kernel.org, Michael Ellerman , linux-riscv@lists.infradead.org, Claudio Imbrenda , kvmarm@lists.cs.columbia.edu, linux-s390@vger.kernel.org, Janosch Frank , Marc Zyngier , Huacai Chen , Aleksandar Markovic , Christian Borntraeger , Chao Gao , Eric Farman , Albert Ou , kvm@vger.kernel.org, Atish Patra , kvmarm@lists.linux.dev, Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Isaku Yamahata , Fabiano Rosas , linux-mips@vger.kernel.org, Palmer Dabbelt , kvm-riscv@lists.infradead.org, Vitaly Kuznetsov , linuxppc-dev@lists.ozlabs.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 19:35, Sean Christopherson wrote: > > It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of > > CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only > > if the actual CPU type matches one of the aforementioned CPU_SUP_*. > > > > E.g. running a kernel built with > > > > CONFIG_CPU_SUP_INTEL=y > > CONFIG_CPU_SUP_AMD=y > > # CONFIG_CPU_SUP_HYGON is not set > > # CONFIG_CPU_SUP_CENTAUR is not set > > # CONFIG_CPU_SUP_ZHAOXIN is not set > > > > on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set > > X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM > > will get unexpected #UDs when trying to enable VMX. > > Oh, I see. Perhaps X86_FEATURE_VMX and X86_FEATURE_SGX should be moved to > one of the software words instead of using cpuid. Nothing that you should > care about for this series though. Or maybe something like this? diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..ebe617ab0b37 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -191,6 +191,8 @@ static void default_init(struct cpuinfo_x86 *c) strcpy(c->x86_model_id, "386"); } #endif + + clear_cpu_cap(c, X86_FEATURE_MSR_IA32_FEAT_CTL); } static const struct cpu_dev default_cpu = { diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index c881bcafba7d..3a7ae67f5a5e 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -72,6 +72,8 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, { X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA }, + { X86_FEATURE_VMX, X86_FEATURE_MSR_IA32_FEAT_CTL }, + { X86_FEATURE_SGX, X86_FEATURE_MSR_IA32_FEAT_CTL }, { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ACA529A8 for ; Thu, 3 Nov 2022 18:58:21 +0000 (UTC) Received: by mail-pf1-f181.google.com with SMTP id d10so2476254pfh.6 for ; Thu, 03 Nov 2022 11:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=OgBlWniGTXEnPcASGuNFCxIZuwOSNaqHJ+Eb2HtkZ3A=; b=crtTNSDLBpNcvDSxofCENmrvtDvGgpUzGCkxI3/S4zR915QtnPiMfGmQ1bfa1+IphI JYKHG76keqoKUqskuvBrM1m0JyELxmvNXlZ4KiPUOKMYgaWfFysvap9RGXI963+2hoeq HHT/GX+S1XBR2PYehjOUxetwVpL78GGV9aYozWyKXyCWQQP6iGe8zgNPOME2bv1qjA9e apMslXORbm1rWkX1K/6OQ1RCG98VSwtHOf2J04nfLy9jITyFIIcn6ieZ9TY4AUm1gsGc eyQU7zbjJP0kGKm2zN/8wgEWv2C3dUA3cPXDwDYFGn1wLuJmRxozNVKQFEnfavfSL6Lx ZqXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=OgBlWniGTXEnPcASGuNFCxIZuwOSNaqHJ+Eb2HtkZ3A=; b=L8KW0qEvh5iqF3jGTzM3CYm955pIWFjkeDZlS6EwV3dcWxagwQvbDojYM7NqJ0iZiu EcFFpX2kyYMZD+IHYZzx3ajI/eksIdFWytT5Y1KHv1S81uMi7gIsfuhV8gkcQtAbKv3B Wg/67ZWs7qgtDHP8ruSwBay9LBfbAhqqaLlz1Aqv/UST/1ND5e2ctA1nj1/edQz8o7JN hPH3dr4MTH6ckCz/zyKoGWR6ZJhKamzSHchxNLnq3Xx2LXSBcKbnMRK0Bt5JNM96JlFg TyU/WA+KGHhcVRpqnvxJ1RKYAYV5Rw5Sc4Uk0T0Yw6VVHnHRfSN91QVn7/nv4TgOsBhm lQAA== X-Gm-Message-State: ACrzQf25pZp0ZFOmPTXMAhxp5+N1VZeaXMzsx/1GXCwIOWswwd3zEHGI sCGdqSdyNiTQTjpZxlRStcMdHQ== X-Google-Smtp-Source: AMsMyM7lUXjnrFRO+e+xTY8enXMXmh/YC+M/IqwbxJRPxqwsuhxb3fUJPK1b1MpOBO3HsUEvz+aKuA== X-Received: by 2002:aa7:81cf:0:b0:561:7d72:73ef with SMTP id c15-20020aa781cf000000b005617d7273efmr31655060pfn.16.1667501900762; Thu, 03 Nov 2022 11:58:20 -0700 (PDT) Received: from google.com (7.104.168.34.bc.googleusercontent.com. [34.168.104.7]) by smtp.gmail.com with ESMTPSA id c20-20020a17090ad91400b00209a12b3879sm309308pjv.37.2022.11.03.11.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 11:58:20 -0700 (PDT) Date: Thu, 3 Nov 2022 18:58:16 +0000 From: Sean Christopherson To: Paolo Bonzini Cc: Marc Zyngier , Huacai Chen , Aleksandar Markovic , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Christian Borntraeger , Janosch Frank , Claudio Imbrenda , Matthew Rosato , Eric Farman , Vitaly Kuznetsov , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Atish Patra , David Hildenbrand , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-kernel@vger.kernel.org, Isaku Yamahata , Fabiano Rosas , Michael Ellerman , Chao Gao , Thomas Gleixner , Yuan Yao Subject: Re: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code Message-ID: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Message-ID: <20221103185816.jyaXFqSuLMNK7XOiKEuLhQnnvMQHltKDqZMg9UHG7oU@z> On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 19:35, Sean Christopherson wrote: > > It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of > > CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only > > if the actual CPU type matches one of the aforementioned CPU_SUP_*. > > > > E.g. running a kernel built with > > > > CONFIG_CPU_SUP_INTEL=y > > CONFIG_CPU_SUP_AMD=y > > # CONFIG_CPU_SUP_HYGON is not set > > # CONFIG_CPU_SUP_CENTAUR is not set > > # CONFIG_CPU_SUP_ZHAOXIN is not set > > > > on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set > > X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM > > will get unexpected #UDs when trying to enable VMX. > > Oh, I see. Perhaps X86_FEATURE_VMX and X86_FEATURE_SGX should be moved to > one of the software words instead of using cpuid. Nothing that you should > care about for this series though. Or maybe something like this? diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..ebe617ab0b37 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -191,6 +191,8 @@ static void default_init(struct cpuinfo_x86 *c) strcpy(c->x86_model_id, "386"); } #endif + + clear_cpu_cap(c, X86_FEATURE_MSR_IA32_FEAT_CTL); } static const struct cpu_dev default_cpu = { diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index c881bcafba7d..3a7ae67f5a5e 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -72,6 +72,8 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, { X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA }, + { X86_FEATURE_VMX, X86_FEATURE_MSR_IA32_FEAT_CTL }, + { X86_FEATURE_SGX, X86_FEATURE_MSR_IA32_FEAT_CTL }, { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BD1DC4332F for ; Thu, 3 Nov 2022 18:58:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2ld1VNhNw+U6bxeGZjgHuZEzsNok9n1UzOTmMBrgJgI=; b=kJk6Fc2BYfCPDn Na/17u2IF9kosw22TCvz0isF4Uas4wM9RYfcfCH9rViSnnptjNqvD3z/aKPYs2bxevbDNKlgmrbsE T18x/x4V0yoobMDrdMxXIyOH0Mr9NhgalWWiUJfqWTqc5eGnvzMOas2EFC44ccSDoJYGYTsSn6M4s z6i/bXNsg6EZ+xWdtBTzE2WdGuOoADpWAfulHagVGm8oRhfhR7O5deEWbqlrVII0pPUSRzxxvJHyT hurdPy70w1zkRVlShhrI3IbXGmjblms+AKCUOlz8CjuipDgV8UskS3OHMREcaZenc0KAl4oJNJlUt UH1G50j9v5Sycqorx0vQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqfQ1-001MjO-I0; Thu, 03 Nov 2022 18:58:25 +0000 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqfPy-001Mi5-Ih for linux-riscv@lists.infradead.org; Thu, 03 Nov 2022 18:58:23 +0000 Received: by mail-pg1-x52a.google.com with SMTP id q1so2449499pgl.11 for ; Thu, 03 Nov 2022 11:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=OgBlWniGTXEnPcASGuNFCxIZuwOSNaqHJ+Eb2HtkZ3A=; b=crtTNSDLBpNcvDSxofCENmrvtDvGgpUzGCkxI3/S4zR915QtnPiMfGmQ1bfa1+IphI JYKHG76keqoKUqskuvBrM1m0JyELxmvNXlZ4KiPUOKMYgaWfFysvap9RGXI963+2hoeq HHT/GX+S1XBR2PYehjOUxetwVpL78GGV9aYozWyKXyCWQQP6iGe8zgNPOME2bv1qjA9e apMslXORbm1rWkX1K/6OQ1RCG98VSwtHOf2J04nfLy9jITyFIIcn6ieZ9TY4AUm1gsGc eyQU7zbjJP0kGKm2zN/8wgEWv2C3dUA3cPXDwDYFGn1wLuJmRxozNVKQFEnfavfSL6Lx ZqXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=OgBlWniGTXEnPcASGuNFCxIZuwOSNaqHJ+Eb2HtkZ3A=; b=q6+qUqXkOfsIuZAdbRT2F4+GAj3BrbebTn7hk7F0i6gu3bwhzQTCXw6QZV60rDbp9z hj3paB6hvBnsEbGeckBI7uPPdK79G1mCCyKx6pbUQkEFWlwt74RnY4CVib7Swqheq3c6 hkaoGdku6LMTprk4IEfltigVz7JrkoyZM6j2I0QDOj6ymRrYSKIIyAG3Fj5VmsbTqzpj CsCs4pHgFJbOBEpO5SBIqF3mp9TKH+LEE5Twek90T0CDrxpF+sKE3ywKpNzAI0diIql3 ULNno2hPDrH9dACpAu9Dofq5dTCKcbI2tgQE1ITBLvxf8fTsbcBX0kXnSRQemu6Yma3e sL2g== X-Gm-Message-State: ACrzQf2ZowkFbHNc1MH5HQi6s+OxrI3zWYzOozGpVD1ZSmleyKbIZ5Kq CWPn9fcH35t5ZsAR0eov6skmig== X-Google-Smtp-Source: AMsMyM7lUXjnrFRO+e+xTY8enXMXmh/YC+M/IqwbxJRPxqwsuhxb3fUJPK1b1MpOBO3HsUEvz+aKuA== X-Received: by 2002:aa7:81cf:0:b0:561:7d72:73ef with SMTP id c15-20020aa781cf000000b005617d7273efmr31655060pfn.16.1667501900762; Thu, 03 Nov 2022 11:58:20 -0700 (PDT) Received: from google.com (7.104.168.34.bc.googleusercontent.com. [34.168.104.7]) by smtp.gmail.com with ESMTPSA id c20-20020a17090ad91400b00209a12b3879sm309308pjv.37.2022.11.03.11.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 11:58:20 -0700 (PDT) Date: Thu, 3 Nov 2022 18:58:16 +0000 From: Sean Christopherson To: Paolo Bonzini Cc: Marc Zyngier , Huacai Chen , Aleksandar Markovic , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Christian Borntraeger , Janosch Frank , Claudio Imbrenda , Matthew Rosato , Eric Farman , Vitaly Kuznetsov , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Atish Patra , David Hildenbrand , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-kernel@vger.kernel.org, Isaku Yamahata , Fabiano Rosas , Michael Ellerman , Chao Gao , Thomas Gleixner , Yuan Yao Subject: Re: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code Message-ID: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221103_115822_624078_E91BDD77 X-CRM114-Status: GOOD ( 19.07 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 19:35, Sean Christopherson wrote: > > It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of > > CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only > > if the actual CPU type matches one of the aforementioned CPU_SUP_*. > > > > E.g. running a kernel built with > > > > CONFIG_CPU_SUP_INTEL=y > > CONFIG_CPU_SUP_AMD=y > > # CONFIG_CPU_SUP_HYGON is not set > > # CONFIG_CPU_SUP_CENTAUR is not set > > # CONFIG_CPU_SUP_ZHAOXIN is not set > > > > on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set > > X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM > > will get unexpected #UDs when trying to enable VMX. > > Oh, I see. Perhaps X86_FEATURE_VMX and X86_FEATURE_SGX should be moved to > one of the software words instead of using cpuid. Nothing that you should > care about for this series though. Or maybe something like this? diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..ebe617ab0b37 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -191,6 +191,8 @@ static void default_init(struct cpuinfo_x86 *c) strcpy(c->x86_model_id, "386"); } #endif + + clear_cpu_cap(c, X86_FEATURE_MSR_IA32_FEAT_CTL); } static const struct cpu_dev default_cpu = { diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index c881bcafba7d..3a7ae67f5a5e 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -72,6 +72,8 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, { X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA }, + { X86_FEATURE_VMX, X86_FEATURE_MSR_IA32_FEAT_CTL }, + { X86_FEATURE_SGX, X86_FEATURE_MSR_IA32_FEAT_CTL }, { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E7FBC433FE for ; Thu, 3 Nov 2022 18:59:21 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4N3CjM4S2Dz3cbV for ; Fri, 4 Nov 2022 05:59:19 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20210112 header.b=crtTNSDL; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=google.com (client-ip=2607:f8b0:4864:20::52a; helo=mail-pg1-x52a.google.com; envelope-from=seanjc@google.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20210112 header.b=crtTNSDL; dkim-atps=neutral Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4N3ChK13DRz3cG1 for ; Fri, 4 Nov 2022 05:58:23 +1100 (AEDT) Received: by mail-pg1-x52a.google.com with SMTP id 78so2444231pgb.13 for ; Thu, 03 Nov 2022 11:58:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=OgBlWniGTXEnPcASGuNFCxIZuwOSNaqHJ+Eb2HtkZ3A=; b=crtTNSDLBpNcvDSxofCENmrvtDvGgpUzGCkxI3/S4zR915QtnPiMfGmQ1bfa1+IphI JYKHG76keqoKUqskuvBrM1m0JyELxmvNXlZ4KiPUOKMYgaWfFysvap9RGXI963+2hoeq HHT/GX+S1XBR2PYehjOUxetwVpL78GGV9aYozWyKXyCWQQP6iGe8zgNPOME2bv1qjA9e apMslXORbm1rWkX1K/6OQ1RCG98VSwtHOf2J04nfLy9jITyFIIcn6ieZ9TY4AUm1gsGc eyQU7zbjJP0kGKm2zN/8wgEWv2C3dUA3cPXDwDYFGn1wLuJmRxozNVKQFEnfavfSL6Lx ZqXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=OgBlWniGTXEnPcASGuNFCxIZuwOSNaqHJ+Eb2HtkZ3A=; b=qtL1e3EoE8YjexuUqJflyLNrJwlGY6Gv05JdyyuBJANnG75WbSxppUq1Ttj0pqUmtm vmJpeOueUyPlRAKwlBEH3AZRi3E2UddvD0NoJx+CFYu6J+v/ZBuU2vp5WKFDLVsrIyIP s/yOQ3IgYRN8+q414eR/ttFPEfJDEdjd48EkQlAkelB3FTZKlxx7eh5yKGhfAhrPL6cK kGg0Y0ysj9TaRQmavm8D3OZK8PMoGdMtgu4Bp2gsbu2cqVmX0OH6B+VpKLlacpcd4okP 8QWEtjJonjFFgmRxRzKhRrtb9UDMgvIsMXmtLEak1NXnMOK3oiNOeyo1cI1ATotn0jm7 xOQQ== X-Gm-Message-State: ACrzQf0Njfsfnmmbl0Ri5LElvNSwn/hv/ktYK25EBOogWcVieC2aWcYo S60VE2CL/tFlT1CN7ymWUKr/lg== X-Google-Smtp-Source: AMsMyM7lUXjnrFRO+e+xTY8enXMXmh/YC+M/IqwbxJRPxqwsuhxb3fUJPK1b1MpOBO3HsUEvz+aKuA== X-Received: by 2002:aa7:81cf:0:b0:561:7d72:73ef with SMTP id c15-20020aa781cf000000b005617d7273efmr31655060pfn.16.1667501900762; Thu, 03 Nov 2022 11:58:20 -0700 (PDT) Received: from google.com (7.104.168.34.bc.googleusercontent.com. [34.168.104.7]) by smtp.gmail.com with ESMTPSA id c20-20020a17090ad91400b00209a12b3879sm309308pjv.37.2022.11.03.11.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 11:58:20 -0700 (PDT) Date: Thu, 3 Nov 2022 18:58:16 +0000 From: Sean Christopherson To: Paolo Bonzini Subject: Re: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code Message-ID: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Rosato , David Hildenbrand , Yuan Yao , Paul Walmsley , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Claudio Imbrenda , kvmarm@lists.cs.columbia.edu, linux-s390@vger.kernel.org, Janosch Frank , Marc Zyngier , Huacai Chen , Aleksandar Markovic , James Morse , Christian Borntraeger , Chao Gao , Eric Farman , Albert Ou , Suzuki K Poulose , kvm@vger.kernel.org, Atish Patra , kvmarm@lists.linux.dev, Thomas Gleixner , Alexandru Elisei , linux-arm-kernel@lists.infradead.org, Isaku Yamahata , Fabiano Rosas , linux-mips@vger.kernel.org, Oliver Upton , Palmer Dabbelt , kvm-riscv@lists.infradead.org, Anup Patel , Vitaly Kuznetsov , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 19:35, Sean Christopherson wrote: > > It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of > > CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only > > if the actual CPU type matches one of the aforementioned CPU_SUP_*. > > > > E.g. running a kernel built with > > > > CONFIG_CPU_SUP_INTEL=y > > CONFIG_CPU_SUP_AMD=y > > # CONFIG_CPU_SUP_HYGON is not set > > # CONFIG_CPU_SUP_CENTAUR is not set > > # CONFIG_CPU_SUP_ZHAOXIN is not set > > > > on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set > > X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM > > will get unexpected #UDs when trying to enable VMX. > > Oh, I see. Perhaps X86_FEATURE_VMX and X86_FEATURE_SGX should be moved to > one of the software words instead of using cpuid. Nothing that you should > care about for this series though. Or maybe something like this? diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..ebe617ab0b37 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -191,6 +191,8 @@ static void default_init(struct cpuinfo_x86 *c) strcpy(c->x86_model_id, "386"); } #endif + + clear_cpu_cap(c, X86_FEATURE_MSR_IA32_FEAT_CTL); } static const struct cpu_dev default_cpu = { diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index c881bcafba7d..3a7ae67f5a5e 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -72,6 +72,8 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, { X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA }, + { X86_FEATURE_VMX, X86_FEATURE_MSR_IA32_FEAT_CTL }, + { X86_FEATURE_SGX, X86_FEATURE_MSR_IA32_FEAT_CTL }, { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF349C4332F for ; Thu, 3 Nov 2022 18:59:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vLnWYeRPqkJZuliyUuzj5W+/y/IwQpoFqiwFdbTIaQc=; b=zqsaJH6uoMT+7n N+worvuQJv25RH6mo3n7YRRr6ZiLLfGkCWHSpVQnWa+/OBQHkxzPct5Gi+ytLftn45EycKkD7oGUT TDp+xOYtGWnI+G0IDNfDmU5EuOJoFvEWJ3ouXcX69NBESdsRrY6PRR8WdTXZDGk4dq7Jew9B3m0Wr aiqTToSCYV/V//KVoP71Sbx2SKa/iSuCbpz78u1nqWVrk1HAYod5cf/TOtAumc7fZOpaclyQ9JwDC n0thfEIXqJOSH9aOFl8d0jdn1+fKbmn5mth2h4VsIraW3HVjpAZmcFlaU7KSqQXuDqF5TK4hK3xHG yP5/5d17p2avxmHBdEwg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqfQ3-001Mk4-AA; Thu, 03 Nov 2022 18:58:27 +0000 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqfPy-001Mi3-Ij for linux-arm-kernel@lists.infradead.org; Thu, 03 Nov 2022 18:58:24 +0000 Received: by mail-pf1-x433.google.com with SMTP id y13so2478209pfp.7 for ; Thu, 03 Nov 2022 11:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=OgBlWniGTXEnPcASGuNFCxIZuwOSNaqHJ+Eb2HtkZ3A=; b=crtTNSDLBpNcvDSxofCENmrvtDvGgpUzGCkxI3/S4zR915QtnPiMfGmQ1bfa1+IphI JYKHG76keqoKUqskuvBrM1m0JyELxmvNXlZ4KiPUOKMYgaWfFysvap9RGXI963+2hoeq HHT/GX+S1XBR2PYehjOUxetwVpL78GGV9aYozWyKXyCWQQP6iGe8zgNPOME2bv1qjA9e apMslXORbm1rWkX1K/6OQ1RCG98VSwtHOf2J04nfLy9jITyFIIcn6ieZ9TY4AUm1gsGc eyQU7zbjJP0kGKm2zN/8wgEWv2C3dUA3cPXDwDYFGn1wLuJmRxozNVKQFEnfavfSL6Lx ZqXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=OgBlWniGTXEnPcASGuNFCxIZuwOSNaqHJ+Eb2HtkZ3A=; b=DIZUUbbaO5P+B9/7S0PB6DWRAfnYI85XsyvrrIuGg4QDh4jvSMiEpHDtB0wQ/Fo5qT yWOff5Ly1Td4+9LuDEtHQdPxbs/98gXm8hRq/+yIOCzRQDtUg+4iaV5eidtgVpZOQsWn AQvnAFrgBDKdlZGEmGhesRDWcTddbiERk7/CLDFBSqnHzRmcQaWywMIYn3nVRI81WNch t9CuHPlTXRZOVDb8fjnofQWnqC8dL+0ZpwenUhjg/VmiFhPXGkWO2J1OB8kX17JZH9ZJ SO1HQlcdE0eowngaSPbVuAugKLLEOeGD129KDVTo41pz2Xofz1b9/CAMixkTQ3NkBRAy z8zA== X-Gm-Message-State: ACrzQf12E6wNu/UfSdEvZNQQtID4bhfBD0ew7lafNuDMJLjvW3aWnpnw m5U6v3wg5QsWwOZotCrid+eHjg== X-Google-Smtp-Source: AMsMyM7lUXjnrFRO+e+xTY8enXMXmh/YC+M/IqwbxJRPxqwsuhxb3fUJPK1b1MpOBO3HsUEvz+aKuA== X-Received: by 2002:aa7:81cf:0:b0:561:7d72:73ef with SMTP id c15-20020aa781cf000000b005617d7273efmr31655060pfn.16.1667501900762; Thu, 03 Nov 2022 11:58:20 -0700 (PDT) Received: from google.com (7.104.168.34.bc.googleusercontent.com. [34.168.104.7]) by smtp.gmail.com with ESMTPSA id c20-20020a17090ad91400b00209a12b3879sm309308pjv.37.2022.11.03.11.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 11:58:20 -0700 (PDT) Date: Thu, 3 Nov 2022 18:58:16 +0000 From: Sean Christopherson To: Paolo Bonzini Cc: Marc Zyngier , Huacai Chen , Aleksandar Markovic , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Christian Borntraeger , Janosch Frank , Claudio Imbrenda , Matthew Rosato , Eric Farman , Vitaly Kuznetsov , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Atish Patra , David Hildenbrand , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-kernel@vger.kernel.org, Isaku Yamahata , Fabiano Rosas , Michael Ellerman , Chao Gao , Thomas Gleixner , Yuan Yao Subject: Re: [PATCH 33/44] KVM: x86: Do VMX/SVM support checks directly in vendor code Message-ID: References: <20221102231911.3107438-1-seanjc@google.com> <20221102231911.3107438-34-seanjc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221103_115822_626610_4325D5E8 X-CRM114-Status: GOOD ( 20.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Nov 03, 2022, Paolo Bonzini wrote: > On 11/3/22 19:35, Sean Christopherson wrote: > > It's technically required. IA32_FEAT_CTL and thus KVM_INTEL depends on any of > > CPU_SUP_{INTEL,CENATUR,ZHAOXIN}, but init_ia32_feat_ctl() is invoked if and only > > if the actual CPU type matches one of the aforementioned CPU_SUP_*. > > > > E.g. running a kernel built with > > > > CONFIG_CPU_SUP_INTEL=y > > CONFIG_CPU_SUP_AMD=y > > # CONFIG_CPU_SUP_HYGON is not set > > # CONFIG_CPU_SUP_CENTAUR is not set > > # CONFIG_CPU_SUP_ZHAOXIN is not set > > > > on a Cenatur or Zhaoxin CPU will leave X86_FEATURE_VMX set but not set > > X86_FEATURE_MSR_IA32_FEAT_CTL. If VMX isn't enabled in MSR_IA32_FEAT_CTL, KVM > > will get unexpected #UDs when trying to enable VMX. > > Oh, I see. Perhaps X86_FEATURE_VMX and X86_FEATURE_SGX should be moved to > one of the software words instead of using cpuid. Nothing that you should > care about for this series though. Or maybe something like this? diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..ebe617ab0b37 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -191,6 +191,8 @@ static void default_init(struct cpuinfo_x86 *c) strcpy(c->x86_model_id, "386"); } #endif + + clear_cpu_cap(c, X86_FEATURE_MSR_IA32_FEAT_CTL); } static const struct cpu_dev default_cpu = { diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index c881bcafba7d..3a7ae67f5a5e 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -72,6 +72,8 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, { X86_FEATURE_PER_THREAD_MBA, X86_FEATURE_MBA }, + { X86_FEATURE_VMX, X86_FEATURE_MSR_IA32_FEAT_CTL }, + { X86_FEATURE_SGX, X86_FEATURE_MSR_IA32_FEAT_CTL }, { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel