From: Thierry Reding <treding@nvidia.com>
To: Ninad Malwade <nmalwade@nvidia.com>
Cc: jonathanh@nvidia.com, linux@roeck-us.net, jdelvare@suse.com,
nicolinc@nvidia.com, rkasirajan@nvidia.com,
linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org
Subject: Re: [PATCH] ina3221: Fix shunt sum critical calculation
Date: Tue, 8 Nov 2022 14:25:47 +0100 [thread overview]
Message-ID: <Y2pY2zuJOII7ko5l@orome> (raw)
In-Reply-To: <20221108044508.23463-1-nmalwade@nvidia.com>
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On Tue, Nov 08, 2022 at 12:45:08PM +0800, Ninad Malwade wrote:
> The shunt sum critical limit register value should be left shifted
> by one bit as its LSB-0 is a reserved bit.
>
> Signed-off-by: Ninad Malwade <nmalwade@nvidia.com>
> ---
> drivers/hwmon/ina3221.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Looks correct:
Reviewed-by: Thierry Reding <treding@nvidia.com>
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next prev parent reply other threads:[~2022-11-08 13:26 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-08 4:45 [PATCH] ina3221: Fix shunt sum critical calculation Ninad Malwade
2022-11-08 13:25 ` Thierry Reding [this message]
2022-11-11 16:27 ` Guenter Roeck
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