From: Catalin Marinas <catalin.marinas@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, will@kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
Jonathan Corbet <corbet@lwn.net>,
Mark Rutland <mark.rutland@arm.com>,
linux-doc@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption
Date: Wed, 9 Nov 2022 19:18:42 +0000 [thread overview]
Message-ID: <Y2v9EiNR40x/cCQm@arm.com> (raw)
In-Reply-To: <20221027023915.1318100-3-anshuman.khandual@arm.com>
On Thu, Oct 27, 2022 at 08:09:15AM +0530, Anshuman Khandual wrote:
> +#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
> +static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
> + unsigned long addr,
> + pte_t *ptep)
> +{
> + pte_t pte = ptep_get_and_clear(vma->vm_mm, addr, ptep);
>
> + if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198)) {
> + /*
> + * Break-before-make (BBM) is required for all user space mappings
> + * when the permission changes from executable to non-executable
> + * in cases where cpu is affected with errata #2645198.
> + */
> + if (pte_user_exec(pte) && cpus_have_const_cap(ARM64_WORKAROUND_2645198))
> + __flush_tlb_range(vma, addr, addr + PAGE_SIZE, PAGE_SIZE, false, 3);
Why not flush_tlb_page() here?
But more importantly, can we not use ptep_clear_flush() instead (and
huge_ptep_clear_flush())? They return the pte and do the TLBI.
--
Catalin
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, will@kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
Jonathan Corbet <corbet@lwn.net>,
Mark Rutland <mark.rutland@arm.com>,
linux-doc@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption
Date: Wed, 9 Nov 2022 19:18:42 +0000 [thread overview]
Message-ID: <Y2v9EiNR40x/cCQm@arm.com> (raw)
In-Reply-To: <20221027023915.1318100-3-anshuman.khandual@arm.com>
On Thu, Oct 27, 2022 at 08:09:15AM +0530, Anshuman Khandual wrote:
> +#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
> +static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
> + unsigned long addr,
> + pte_t *ptep)
> +{
> + pte_t pte = ptep_get_and_clear(vma->vm_mm, addr, ptep);
>
> + if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198)) {
> + /*
> + * Break-before-make (BBM) is required for all user space mappings
> + * when the permission changes from executable to non-executable
> + * in cases where cpu is affected with errata #2645198.
> + */
> + if (pte_user_exec(pte) && cpus_have_const_cap(ARM64_WORKAROUND_2645198))
> + __flush_tlb_range(vma, addr, addr + PAGE_SIZE, PAGE_SIZE, false, 3);
Why not flush_tlb_page() here?
But more importantly, can we not use ptep_clear_flush() instead (and
huge_ptep_clear_flush())? They return the pte and do the TLBI.
--
Catalin
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next prev parent reply other threads:[~2022-11-09 19:18 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-27 2:39 [PATCH 0/2] arm64: errata: Workaround Cortex-A715 errata #2645198 Anshuman Khandual
2022-10-27 2:39 ` Anshuman Khandual
2022-10-27 2:39 ` [PATCH 1/2] arm64: Add Cortex-715 CPU part definition Anshuman Khandual
2022-10-27 2:39 ` Anshuman Khandual
2022-10-27 2:39 ` [PATCH 2/2] arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption Anshuman Khandual
2022-10-27 2:39 ` Anshuman Khandual
2022-11-09 19:18 ` Catalin Marinas [this message]
2022-11-09 19:18 ` Catalin Marinas
2022-11-10 3:15 ` Anshuman Khandual
2022-11-10 3:15 ` Anshuman Khandual
2022-11-11 22:36 ` Catalin Marinas
2022-11-11 22:36 ` Catalin Marinas
2022-11-12 13:52 ` Anshuman Khandual
2022-11-12 13:52 ` Anshuman Khandual
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