From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: linux-renesas-soc@vger.kernel.org,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Subject: Re: [RFC PATCH] clocksource/drivers/sh_cmt: access registers according to spec
Date: Fri, 18 Nov 2022 08:30:30 +0100 [thread overview]
Message-ID: <Y3c0lpl8zzKMnRPO@ninjato> (raw)
In-Reply-To: <CAMuHMdUVmapwN_OHpn4RtQebZCbEi3avka+2MuWpCk59g5UyLA@mail.gmail.com>
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> unsigned int (everywhere)?
> Yes, this is the result of a long-by-long division, but it should be
> a small value anyway.
OK.
> > + /* Tests showed that we need to wait 3 clocks here */
> > + unsigned long cmcnt_delay = ch->cmt->reg_delay * 3 / 2;
>
> DIV_ROUND_UP()
Really here? reg_delay is ensured to be a multiple of two...
> > + /* We shall wait 2 input clks after register writes */
> > + if (cmt->info->model >= SH_CMT_48BIT) // FIXME: Really not needed for older ones?
> > + cmt->reg_delay = 2000000UL / rate + 1;
... but here it would make a lot of sense!
> > + cmt->rate = cmt->info->width == 16 ? rate / 512 : rate / 8;
>
> cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8);
OK. I had it without the parens and it looked ugly. With parens it looks
good.
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next prev parent reply other threads:[~2022-11-18 7:30 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-16 20:21 [RFC PATCH] clocksource/drivers/sh_cmt: access registers according to spec Wolfram Sang
2022-11-16 21:10 ` Wolfram Sang
2022-11-17 8:45 ` Geert Uytterhoeven
2022-11-18 7:30 ` Wolfram Sang [this message]
2022-11-18 8:25 ` Geert Uytterhoeven
2022-11-18 8:30 ` Wolfram Sang
2022-11-18 8:46 ` Geert Uytterhoeven
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