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b=EPoZ8lQFM7WnkD2kn0+DJaKIC/I4Doa5nNO8dv9j1wpe lAUBu58kfgh1TEe3UUUl3PagVLy8pilWuqq69VerOFyVzjsb8iNKnzTEJKQBISwV OeGnDRbNAxAparwTpuK+VZ3VrDc3UVAioRNtWOdVv9kCa5qkYfKGEEg6gZ1OpFKg XrIiIqGnkSurdZRAp7p0BKNo2wfDg/is2w7q4398LIbm53PaPpz8WLJxAiB8R/58 xooGdbXh71IqjXJ6kD+vBkI2UQZ4Hr171Uo11dzx+yn17EL95+fqlgp2aYwqKdAH npDYSs4PfHsOMsUCTqv607FyWarOQgf/GlKQbw55+g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrhedtgdegjecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpeffhffvvefukfhfgggtuggjsehgtderredttdejnecuhfhrohhmpeforghrvghk ucforghrtgiihihkohifshhkihdqifpkrhgvtghkihcuoehmrghrmhgrrhgvkhesihhnvh hishhisghlvghthhhinhhgshhlrggsrdgtohhmqeenucggtffrrghtthgvrhhnpefgudel teefvefhfeehieetleeihfejhfeludevteetkeevtedtvdegueetfeejudenucevlhhush htvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehmrghrmhgrrhgvkhes ihhnvhhishhisghlvghthhhinhhgshhlrggsrdgtohhm X-ME-Proxy: Feedback-ID: i1568416f:Fastmail Date: Fri, 18 Nov 2022 14:00:23 +0100 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: Andrew Cooper , Roger Pau =?utf-8?B?TW9ubsOp?= , Wei Liu , xen-devel@lists.xenproject.org Subject: Re: [PATCH 2/2] x86/msi: Allow writes to registers on the same page as MSI-X table Message-ID: References: <20221114192100.1539267-1-marmarek@invisiblethingslab.com> <20221114192100.1539267-2-marmarek@invisiblethingslab.com> <15138618-5cb0-8304-a56b-cb787e187772@suse.com> <9d034957-822c-74ba-9aea-0944cc456870@suse.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="GusqaJC/8lAeSwP9" Content-Disposition: inline In-Reply-To: <9d034957-822c-74ba-9aea-0944cc456870@suse.com> --GusqaJC/8lAeSwP9 Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Fri, 18 Nov 2022 14:00:23 +0100 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: Andrew Cooper , Roger Pau =?utf-8?B?TW9ubsOp?= , Wei Liu , xen-devel@lists.xenproject.org Subject: Re: [PATCH 2/2] x86/msi: Allow writes to registers on the same page as MSI-X table On Fri, Nov 18, 2022 at 01:33:39PM +0100, Jan Beulich wrote: > On 18.11.2022 13:19, Marek Marczykowski-G=C3=B3recki wrote: > > On Fri, Nov 18, 2022 at 08:20:14AM +0100, Jan Beulich wrote: > >> On 17.11.2022 18:31, Marek Marczykowski-G=C3=B3recki wrote: > >>> On Thu, Nov 17, 2022 at 05:34:36PM +0100, Jan Beulich wrote: > >>>> Which in turn raises the question: Do you need to handle reads > >>>> in the new code in the first place? > >>> > >>> The page not being mapped is also the reason why I do need to handle > >>> reads too. > >> > >> Just for my own clarity: You mean "not mapped to qemu" here? > >=20 > > No, to the HVM domain (in p2m). Xen (outside of MSI-X specific code for > > HVM) doesn't know where those reads should be from. >=20 > Hmm, I was expecting them to be mapped r/o to the guest, but perhaps I'm > misremembering. Clearly both ept_p2m_type_to_flags() and > p2m_type_to_flags() take mmio_ro_ranges into consideration, which is > what I was basing my understanding on (without having looked at other > places in detail). Qemu doesn't map the page (using xc_domain_memory_mapping()) where MSI-X table lives. I tried to modify this part, but it resulted in EPT violation on write attempt (and my emulation code wasn't called at all). --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --GusqaJC/8lAeSwP9 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmN3gecACgkQ24/THMrX 1yz9yQf/QS1FJclofzjtQVr6ZaCqzuNX4dMjEJKWEjojyd4EvPlWBZ2qs+IDtKjS hEAn+pfKe/2y089giG+Dh5wvZwnONZobxeQ14Vg2jTeV7rIgSG5SVmPhZkfU4KIQ 1ABhPg+EAdRXklbCb6SoIWSYcLHRg44VsYURuMrazXbT3/VKGhT5eLd6xgc1LttK 2P1gy4J76x1rLGoPF5YMCMpD19tczQcQdKWtGMoZFI9d/Lu6YlntHwllf+AUkShe CbMrauSkNajQrqOt6vCDifavzJur6khROYRVV8FEypgy+FTgWgkIbeWWYB2dbDlu uwS1bzatLFE3SnW42Fyqyfdr0IAxtA== =eYPR -----END PGP SIGNATURE----- --GusqaJC/8lAeSwP9--